intel/compiler: Pass shader_stats for each SIMD mode
Passing shader_stats to the fs_generator constructor means that the SIMD8 shader stats from the visitor (such as the scheduler mode) will be reported out for the SIMD16/SIMD32 versions as well. As you can see, we are now passing 'shader_stats' and 'stats' to generate_code(), which is obviously odd looking. Ian rebased and committed an old patch of mine which added the shader_stats struct on July 30 in commitdabb5d4bee(i965/fs: Add a shader_stats struct.) and shortly after on August 12 Jason added the brw_compile_stats struct in commit134607760a(intel/compiler: Fill a compiler statistics struct). I'd like to combine the two, but I'm not sure how. shader_stats is an input to generate_code() while brw_compile_stats is an output and is only used by the Vulkan driver. Leave it as is for now... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
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@@ -8601,6 +8601,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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brw_compute_flat_inputs(prog_data, shader);
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cfg_t *simd8_cfg = NULL, *simd16_cfg = NULL, *simd32_cfg = NULL;
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struct shader_stats v8_shader_stats, v16_shader_stats, v32_shader_stats;
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fs_visitor v8(compiler, log_data, mem_ctx, &key->base,
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&prog_data->base, shader, 8,
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@@ -8612,6 +8613,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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return NULL;
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} else if (likely(!(INTEL_DEBUG & DEBUG_NO8))) {
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simd8_cfg = v8.cfg;
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v8_shader_stats = v8.shader_stats;
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prog_data->base.dispatch_grf_start_reg = v8.payload.num_regs;
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prog_data->reg_blocks_8 = brw_register_blocks(v8.grf_used);
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}
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@@ -8639,6 +8641,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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v16.fail_msg);
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} else {
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simd16_cfg = v16.cfg;
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v16_shader_stats = v16.shader_stats;
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prog_data->dispatch_grf_start_reg_16 = v16.payload.num_regs;
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prog_data->reg_blocks_16 = brw_register_blocks(v16.grf_used);
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}
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@@ -8659,6 +8662,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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v32.fail_msg);
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} else {
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simd32_cfg = v32.cfg;
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v32_shader_stats = v32.shader_stats;
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prog_data->dispatch_grf_start_reg_32 = v32.payload.num_regs;
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prog_data->reg_blocks_32 = brw_register_blocks(v32.grf_used);
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}
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@@ -8712,8 +8716,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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}
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fs_generator g(compiler, log_data, mem_ctx, &prog_data->base,
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v8.shader_stats, v8.runtime_check_aads_emit,
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MESA_SHADER_FRAGMENT);
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v8.runtime_check_aads_emit, MESA_SHADER_FRAGMENT);
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if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
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g.enable_debug(ralloc_asprintf(mem_ctx, "%s fragment shader %s",
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@@ -8724,19 +8727,19 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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if (simd8_cfg) {
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prog_data->dispatch_8 = true;
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g.generate_code(simd8_cfg, 8, stats);
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g.generate_code(simd8_cfg, 8, v8_shader_stats, stats);
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stats = stats ? stats + 1 : NULL;
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}
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if (simd16_cfg) {
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prog_data->dispatch_16 = true;
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prog_data->prog_offset_16 = g.generate_code(simd16_cfg, 16, stats);
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prog_data->prog_offset_16 = g.generate_code(simd16_cfg, 16, v16_shader_stats, stats);
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stats = stats ? stats + 1 : NULL;
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}
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if (simd32_cfg) {
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prog_data->dispatch_32 = true;
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prog_data->prog_offset_32 = g.generate_code(simd32_cfg, 32, stats);
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prog_data->prog_offset_32 = g.generate_code(simd32_cfg, 32, v32_shader_stats, stats);
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stats = stats ? stats + 1 : NULL;
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}
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@@ -8979,8 +8982,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
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*error_str = ralloc_strdup(mem_ctx, fail_msg);
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} else {
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fs_generator g(compiler, log_data, mem_ctx, &prog_data->base,
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v->shader_stats, v->runtime_check_aads_emit,
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MESA_SHADER_COMPUTE);
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v->runtime_check_aads_emit, MESA_SHADER_COMPUTE);
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if (INTEL_DEBUG & DEBUG_CS) {
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char *name = ralloc_asprintf(mem_ctx, "%s compute shader %s",
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src_shader->info.label ?
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@@ -8989,7 +8991,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
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g.enable_debug(name);
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}
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g.generate_code(v->cfg, prog_data->simd_size, stats);
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g.generate_code(v->cfg, prog_data->simd_size, v->shader_stats, stats);
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ret = g.get_assembly();
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}
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