iris: Allow PIPE_CONTROL with Stall at Scoreboard and RT flush
It's nonsensical, but not illegal, and mandatory on Icelake
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@@ -4302,7 +4302,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, uint32_t flags,
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PIPE_CONTROL_WRITE_TIMESTAMP)));
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}
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if (flags & PIPE_CONTROL_STALL_AT_SCOREBOARD) {
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if (GEN_GEN < 11 && (flags & PIPE_CONTROL_STALL_AT_SCOREBOARD)) {
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/* From the PIPE_CONTROL instruction table, bit 1:
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*
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* "This bit is ignored if Depth Stall Enable is set.
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@@ -4311,6 +4311,10 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, uint32_t flags,
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*
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* We assert that the caller doesn't do this combination, to try and
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* prevent mistakes. It shouldn't hurt the GPU, though.
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*
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* We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
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* and "Render Target Flush" combo is explicitly required for BTI
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* update workarounds.
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*/
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assert(!(flags & (PIPE_CONTROL_DEPTH_STALL |
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PIPE_CONTROL_RENDER_TARGET_FLUSH)));
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