brw: Eliminate the BTI source from MEMORY_FENCE/INTERLOCK opcodes
Memory fences do not refer to an element of a binding table. Rather, the reason we had "BTI" in these opcodes was to distinguish what in modern terms are called UGM (untyped memory data cache) vs. SLM (cross-thread shared local memory) fences. Icelake and older platforms used the "data cache" SFID for both purposes, distinguishing them by having a special binding table index, 254, meaning "this is actually SLM access". This is where the notion that fences had BTIs came in. (In fact, prior to Icelake, separate SLM fences were not a thing, so BTI wasn't used there either.) To avoid confusion about BTI being involved, we choose a simpler lie: we have Icelake SLM fences target GFX12_SFID_SLM (like modern platforms would), even though it didn't really exist back then. Later lowering code sets it back to the correct Data Cache SFID with magic SLM binding table index. This eliminates BTI everywhere and an unnecessary source. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33297>
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@@ -1196,7 +1196,6 @@ brw_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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case SHADER_OPCODE_INTERLOCK:
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case SHADER_OPCODE_MEMORY_FENCE: {
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assert(src[1].file == IMM);
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assert(src[2].file == IMM);
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const enum opcode send_op = inst->opcode == SHADER_OPCODE_INTERLOCK ?
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BRW_OPCODE_SENDC : BRW_OPCODE_SEND;
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@@ -1204,8 +1203,7 @@ brw_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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brw_memory_fence(p, dst, src[0], send_op,
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brw_message_target(inst->sfid),
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inst->desc,
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/* commit_enable */ src[1].ud,
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/* bti */ src[2].ud);
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/* commit_enable */ src[1].ud);
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send_count++;
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break;
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}
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