brw: Eliminate the BTI source from MEMORY_FENCE/INTERLOCK opcodes
Memory fences do not refer to an element of a binding table. Rather, the reason we had "BTI" in these opcodes was to distinguish what in modern terms are called UGM (untyped memory data cache) vs. SLM (cross-thread shared local memory) fences. Icelake and older platforms used the "data cache" SFID for both purposes, distinguishing them by having a special binding table index, 254, meaning "this is actually SLM access". This is where the notion that fences had BTIs came in. (In fact, prior to Icelake, separate SLM fences were not a thing, so BTI wasn't used there either.) To avoid confusion about BTI being involved, we choose a simpler lie: we have Icelake SLM fences target GFX12_SFID_SLM (like modern platforms would), even though it didn't really exist back then. Later lowering code sets it back to the correct Data Cache SFID with magic SLM binding table index. This eliminates BTI everywhere and an unnecessary source. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33297>
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@@ -4967,7 +4967,7 @@ increment_a64_address(const brw_builder &_bld, brw_reg address, uint32_t v, bool
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static brw_reg
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emit_fence(const brw_builder &bld, enum opcode opcode,
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uint8_t sfid, uint32_t desc,
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bool commit_enable, uint8_t bti)
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bool commit_enable)
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{
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const struct intel_device_info *devinfo = bld.shader->devinfo;
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@@ -4976,8 +4976,7 @@ emit_fence(const brw_builder &bld, enum opcode opcode,
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brw_reg dst = bld.vgrf(BRW_TYPE_UD);
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brw_inst *fence = bld.emit(opcode, dst, brw_vec8_grf(0, 0),
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brw_imm_ud(commit_enable),
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brw_imm_ud(bti));
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brw_imm_ud(commit_enable));
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fence->sfid = sfid;
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fence->desc = desc;
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fence->size_written = commit_enable ? REG_SIZE * reg_unit(devinfo) : 0;
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@@ -5993,15 +5992,13 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb,
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if (ugm_fence) {
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fence_regs[fence_regs_count++] =
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emit_fence(ubld1, opcode, GFX12_SFID_UGM, desc,
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true /* commit_enable */,
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0 /* bti; ignored for LSC */);
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true /* commit_enable */);
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}
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if (tgm_fence) {
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fence_regs[fence_regs_count++] =
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emit_fence(ubld1, opcode, GFX12_SFID_TGM, desc,
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true /* commit_enable */,
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0 /* bti; ignored for LSC */);
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true /* commit_enable */);
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}
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if (slm_fence) {
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@@ -6016,31 +6013,31 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb,
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}
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fence_regs[fence_regs_count++] =
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emit_fence(ubld1, opcode, GFX12_SFID_SLM, desc,
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true /* commit_enable */,
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0 /* BTI; ignored for LSC */);
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true /* commit_enable */);
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}
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if (urb_fence) {
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assert(opcode == SHADER_OPCODE_MEMORY_FENCE);
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fence_regs[fence_regs_count++] =
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emit_fence(ubld1, opcode, BRW_SFID_URB, desc,
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true /* commit_enable */,
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0 /* BTI; ignored for LSC */);
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true /* commit_enable */);
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}
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} else if (devinfo->ver >= 11) {
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if (tgm_fence || ugm_fence || urb_fence) {
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fence_regs[fence_regs_count++] =
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emit_fence(ubld1, opcode, GFX7_SFID_DATAPORT_DATA_CACHE, 0,
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true /* commit_enable HSD ES # 1404612949 */,
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0 /* BTI = 0 means data cache */);
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true /* commit_enable HSD ES # 1404612949 */);
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}
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if (slm_fence) {
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assert(opcode == SHADER_OPCODE_MEMORY_FENCE);
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/* We use the "SLM" SFID here even though it doesn't exist;
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* the logical send lowering will replace it with the SLM
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* special binding table index and the normal DATA_CACHE SFID.
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*/
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fence_regs[fence_regs_count++] =
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emit_fence(ubld1, opcode, GFX7_SFID_DATAPORT_DATA_CACHE, 0,
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true /* commit_enable HSD ES # 1404612949 */,
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GFX7_BTI_SLM);
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emit_fence(ubld1, opcode, GFX12_SFID_SLM, 0,
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true /* commit_enable HSD ES # 1404612949 */);
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}
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} else {
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/* Simulation also complains on Gfx9 if we do not enable commit.
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@@ -6052,7 +6049,7 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb,
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if (tgm_fence || ugm_fence || slm_fence || urb_fence) {
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fence_regs[fence_regs_count++] =
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emit_fence(ubld1, opcode, GFX7_SFID_DATAPORT_DATA_CACHE, 0,
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commit_enable, 0 /* BTI */);
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commit_enable);
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}
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}
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