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freedreno/a6xx: always use reg64 for address registers (no LO/HI)

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Reduce noise in a6xx.xml by removing LO/HI versions of address registers.

Also fix type="address" registers in register packing (use bit size instead
of checking for "waddress" to use qword)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8423>
This commit is contained in:
Jonathan Marek
2021-01-11 13:48:24 -05:00
committed by Marge Bot
parent b15d4484f8
commit b94c652afe
16 changed files with 516 additions and 582 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/freedreno/.gitlab-ci/reference/crash.log
+270 -270
View File
File diff suppressed because it is too large Load Diff
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+50 -50
View File
@@ -208,22 +208,22 @@ t4 write RB_LRZ_CNTL (8898)
0000000001058214: 0000: 40889801 00000000
t4 write SP_TP_BORDER_COLOR_BASE_ADDR (b302)
SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
000000000105821c: 0000: 48b30202 01011000 00000000
t4 write SP_PS_TP_BORDER_COLOR_BASE_ADDR (b180)
SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0
0000000001058228: 0000: 40b18002 01011000 00000000
t4 write VSC_DRAW_STRM_SIZE_ADDRESS_LO (0c03)
VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x10fd000
t4 write VSC_DRAW_STRM_SIZE_ADDRESS (0c03)
VSC_DRAW_STRM_SIZE_ADDRESS: 0x10fd000
VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
0000000001058234: 0000: 480c0302 010fd000 00000000
t4 write VSC_PRIM_STRM_ADDRESS_LO (0c30)
VSC_PRIM_STRM_ADDRESS_LO: 0x105c000
t4 write VSC_PRIM_STRM_ADDRESS (0c30)
VSC_PRIM_STRM_ADDRESS: 0x105c000
VSC_PRIM_STRM_ADDRESS_HI: 0
0000000001058240: 0000: 480c3002 0105c000 00000000
t4 write VSC_DRAW_STRM_ADDRESS_LO (0c34)
VSC_DRAW_STRM_ADDRESS_LO: 0x10dc800
t4 write VSC_DRAW_STRM_ADDRESS (0c34)
VSC_DRAW_STRM_ADDRESS: 0x10dc800
VSC_DRAW_STRM_ADDRESS_HI: 0
000000000105824c: 0000: 400c3402 010dc800 00000000
t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
@@ -263,12 +263,12 @@ t4 write GRAS_2D_DST_TL (8405)
00000000010582ac: 0000: 48840502 00000000 00ff00ff
t4 write RB_2D_DST_INFO (8c17)
RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
RB_2D_DST_LO: 0x1013000
RB_2D_DST: 0x1013000
RB_2D_DST_HI: 0
RB_2D_DST_PITCH: 1024
00000000010582b8: 0000: 408c1704 00001330 01013000 00000000 00000010
t4 write RB_2D_DST_FLAGS_LO (8c20)
RB_2D_DST_FLAGS_LO: 0x1012000
t4 write RB_2D_DST_FLAGS (8c20)
RB_2D_DST_FLAGS: 0x1012000
RB_2D_DST_FLAGS_HI: 0
RB_2D_DST_FLAGS_PITCH: 64 | 0x4000
00000000010582cc: 0000: 488c2083 01012000 00000000 00004001
@@ -277,11 +277,11 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
mode: (null)
skip_ib2: g=0, l=0
draw[0] register values
!+ 010fd000 VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x10fd000
!+ 010fd000 VSC_DRAW_STRM_SIZE_ADDRESS: 0x10fd000
+ 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
!+ 0105c000 VSC_PRIM_STRM_ADDRESS_LO: 0x105c000
!+ 0105c000 VSC_PRIM_STRM_ADDRESS: 0x105c000
+ 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0
!+ 010dc800 VSC_DRAW_STRM_ADDRESS_LO: 0x10dc800
!+ 010dc800 VSC_DRAW_STRM_ADDRESS: 0x10dc800
+ 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0
!+ 03200000 UCHE_UNKNOWN_0E12: 0x3200000
!+ 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 }
@@ -311,10 +311,10 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
!+ 10f03080 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 }
+ 00000000 RB_2D_UNKNOWN_8C01: 0
!+ 00001330 RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
!+ 01013000 RB_2D_DST_LO: 0x1013000
!+ 01013000 RB_2D_DST: 0x1013000
+ 00000000 RB_2D_DST_HI: 0
!+ 00000010 RB_2D_DST_PITCH: 1024
!+ 01012000 RB_2D_DST_FLAGS_LO: 0x1012000
!+ 01012000 RB_2D_DST_FLAGS: 0x1012000
+ 00000000 RB_2D_DST_FLAGS_HI: 0
!+ 00004001 RB_2D_DST_FLAGS_PITCH: 64 | 0x4000
+ 00000000 RB_2D_SRC_SOLID_C0: 0
@@ -353,11 +353,11 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
!+ 00000008 SP_UNKNOWN_AE04: 0x8
!+ 0000003f SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
!+ 01011000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
+ 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0
+ 00000000 SP_UNKNOWN_B182: 0
+ 00000000 SP_UNKNOWN_B183: 0
!+ 01011000 SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
+ 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
!+ 000000a2 SP_TP_UNKNOWN_B309: 0xa2
!+ 00100000 SP_UNKNOWN_B600: 0x100000
!+ 00000044 SP_UNKNOWN_B605: 0x44
@@ -466,12 +466,12 @@ t4 write RB_BLIT_INFO (88e3)
t4 write RB_BLIT_DST_INFO (88d7)
RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
RB_BLIT_DST: 0x1013000
RB_BLIT_DST+0x1: 0
RB_BLIT_DST_HI: 0
RB_BLIT_DST_PITCH: 1024
000000000115e028: 0000: 4888d704 00001807 01013000 00000000 00000010
t4 write RB_BLIT_FLAG_DST (88dc)
RB_BLIT_FLAG_DST: 0x1012000
RB_BLIT_FLAG_DST+0x1: 0
RB_BLIT_FLAG_DST_HI: 0
RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
000000000115e03c: 0000: 4088dc83 01012000 00000000 00004001
t4 write RB_BLIT_BASE_GMEM (88d6)
@@ -498,10 +498,10 @@ t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
+ 00000000 RB_BLIT_BASE_GMEM: 0
!+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
!+ 01013000 RB_BLIT_DST: 0x1013000
+ 00000000 RB_BLIT_DST+0x1: 0
+ 00000000 RB_BLIT_DST_HI: 0
!+ 00000010 RB_BLIT_DST_PITCH: 1024
!+ 01012000 RB_BLIT_FLAG_DST: 0x1012000
+ 00000000 RB_BLIT_FLAG_DST+0x1: 0
+ 00000000 RB_BLIT_FLAG_DST_HI: 0
!+ 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
!+ 00000003 RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 }
!+ 7c400000 RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM }
@@ -521,18 +521,18 @@ t4 write RB_DEPTH_BUFFER_INFO (8872)
RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
RB_DEPTH_BUFFER_PITCH: 0
RB_DEPTH_BUFFER_ARRAY_PITCH: 0
RB_DEPTH_BUFFER_BASE_LO: 0
RB_DEPTH_BUFFER_BASE: 0
RB_DEPTH_BUFFER_BASE_HI: 0
RB_DEPTH_BUFFER_BASE_GMEM: 0
000000000115e074: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000
t4 write GRAS_SU_DEPTH_BUFFER_INFO (8098)
GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
000000000115e090: 0000: 48809801 00000000
t4 write GRAS_LRZ_BUFFER_BASE_LO (8103)
GRAS_LRZ_BUFFER_BASE_LO: 0
t4 write GRAS_LRZ_BUFFER_BASE (8103)
GRAS_LRZ_BUFFER_BASE: 0
GRAS_LRZ_BUFFER_BASE_HI: 0
GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
000000000115e098: 0000: 48810385 00000000 00000000 00000000 00000000 00000000
t4 write RB_STENCIL_INFO (8881)
@@ -542,15 +542,15 @@ t4 write RB_MRT[0].BUF_INFO (8822)
RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX }
RB_MRT[0].PITCH: 1024
RB_MRT[0].ARRAY_PITCH: 262144
RB_MRT[0].BASE_LO: 0x1013000
RB_MRT[0].BASE: 0x1013000
RB_MRT[0].BASE_HI: 0
RB_MRT[0].BASE_GMEM: 0
000000000115e0b8: 0000: 48882286 00000330 00000010 00001000 01013000 00000000 00000000
t4 write SP_FS_MRT[0].REG (a996)
SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
000000000115e0d4: 0000: 48a99601 00000030
t4 write RB_MRT_FLAG_BUFFER[0].ADDR_LO (8903)
RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0x1012000
t4 write RB_MRT_FLAG_BUFFER[0].ADDR (8903)
RB_MRT_FLAG_BUFFER[0].ADDR: 0x1012000
RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
000000000115e0dc: 0000: 40890383 01012000 00000000 00004001
@@ -792,9 +792,8 @@ t4 write SP_VS_CONFIG (a823)
t4 write HLSQ_VS_CNTL (b800)
HLSQ_VS_CNTL: { CONSTLEN = 4 | ENABLED }
000000000105419c: 0000: 48b80001 00000101
t4 write SP_VS_OBJ_START_LO (a81c)
SP_VS_OBJ_START_LO: 0x1054000 base=1054000, offset=0, size=12288
SP_VS_OBJ_START_HI: 0 base=1054000, offset=0, size=12288
t4 write SP_VS_OBJ_START (a81c)
SP_VS_OBJ_START: 0x1054000 base=1054000, offset=0, size=12288
0000000001054000: 0000: 00080009 42bc080b 10040004 64858008 10050005 64858009 10050006 6485800a
0000000001054020: 0020: 10040007 6485800b 00000000 03000000 00000000 00000000 00000000 00000000
*
@@ -816,6 +815,7 @@ t4 write SP_VS_OBJ_START_LO (a81c)
- shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen
- shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
SP_VS_OBJ_START_HI: 0
00000000010541a4: 0000: 48a81c02 01054000 00000000
t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
@@ -872,9 +872,8 @@ t4 write SP_FS_CONFIG (ab04)
t4 write HLSQ_FS_CNTL (bb10)
HLSQ_FS_CNTL: { CONSTLEN = 0 | ENABLED }
0000000001054224: 0000: 40bb1001 00000100
t4 write SP_FS_OBJ_START_LO (a983)
SP_FS_OBJ_START_LO: 0x1054080 base=1054000, offset=128, size=12288
SP_FS_OBJ_START_HI: 0 base=1054000, offset=128, size=12288
t4 write SP_FS_OBJ_START (a983)
SP_FS_OBJ_START: 0x1054080 base=1054000, offset=128, size=12288
0000000001054080: 0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005
00000000010540a0: 0020: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
@@ -894,6 +893,7 @@ t4 write SP_FS_OBJ_START_LO (a983)
- shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
SP_FS_OBJ_START_HI: 0
000000000105422c: 0000: 40a98302 01054080 00000000
t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 1 }
@@ -1071,7 +1071,7 @@ t4 write RB_DEPTH_PLANE_CNTL (8870)
000000000115c070: 0000: 40a01083 01053000 00000000 00000318
t4 write VFD_FETCH[0].BASE (a010)
VFD_FETCH[0].BASE: 0x1053000
VFD_FETCH[0].BASE+0x1: 0
VFD_FETCH[0].BASE_HI: 0
VFD_FETCH[0].SIZE: 792
000000000115c070: 0000: 40a01083 01053000 00000000 00000318
group_id: 4
@@ -1341,10 +1341,10 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
+ 00000000 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 }
!+ 00ff00ff GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 255 | Y = 255 }
+ 00000000 GRAS_UNKNOWN_8101: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
+ 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
+ 00000000 GRAS_SAMPLE_CNTL: { 0 }
!+ 00010010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0x1 }
@@ -1363,7 +1363,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
!+ 00000330 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX }
!+ 00000010 RB_MRT[0].PITCH: 1024
!+ 00001000 RB_MRT[0].ARRAY_PITCH: 262144
!+ 01013000 RB_MRT[0].BASE_LO: 0x1013000
!+ 01013000 RB_MRT[0].BASE: 0x1013000
+ 00000000 RB_MRT[0].BASE_HI: 0
+ 00000000 RB_MRT[0].BASE_GMEM: 0
!+ dffe8440 RB_BLEND_RED_F32: -36679707902607360000.000000
@@ -1377,7 +1377,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
+ 00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
+ 00000000 RB_DEPTH_BUFFER_PITCH: 0
+ 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_LO: 0
+ 00000000 RB_DEPTH_BUFFER_BASE: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_HI: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0
+ 00000000 RB_Z_BOUNDS_MIN: 0.000000
@@ -1392,7 +1392,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
+ 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
+ 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
+ 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
!+ 01012000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0x1012000
!+ 01012000 RB_MRT_FLAG_BUFFER[0].ADDR: 0x1012000
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
!+ 00004001 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
!+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
@@ -1435,7 +1435,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 }
+ 00000000 VFD_CONTROL_6: { 0 }
!+ 01053000 VFD_FETCH[0].BASE: 0x1053000
+ 00000000 VFD_FETCH[0].BASE+0x1: 0
+ 00000000 VFD_FETCH[0].BASE_HI: 0
!+ 00000318 VFD_FETCH[0].SIZE: 792
!+ 00000024 VFD_FETCH[0].STRIDE: 36
!+ c8200000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
@@ -1451,8 +1451,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
!+ 00000002 SP_VS_PRIMITIVE_CNTL: { OUT = 2 }
!+ 0f000f08 SP_VS_OUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf }
!+ 00000400 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 0 | OUTLOC3 = 0 }
!+ 01054000 SP_VS_OBJ_START_LO: 0x1054000 base=1054000, offset=0, size=12288
+ 00000000 SP_VS_OBJ_START_HI: 0 base=1054000, offset=0, size=12288
!+ 01054000 SP_VS_OBJ_START: 0x1054000 base=1054000, offset=0, size=12288
0000000001054000: 0000: 00080009 42bc080b 10040004 64858008 10050005 64858009 10050006 6485800a
0000000001054020: 0020: 10040007 6485800b 00000000 03000000 00000000 00000000 00000000 00000000
*
@@ -1474,6 +1473,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
- shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen
- shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000000 SP_VS_OBJ_START_HI: 0
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
@@ -1481,8 +1481,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 81500100 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | VARYING | MERGEDREGS | 0x1000000 }
!+ 01054080 SP_FS_OBJ_START_LO: 0x1054080 base=1054000, offset=128, size=12288
+ 00000000 SP_FS_OBJ_START_HI: 0 base=1054000, offset=128, size=12288
!+ 01054080 SP_FS_OBJ_START: 0x1054080 base=1054000, offset=128, size=12288
0000000001054080: 0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005
00000000010540a0: 0020: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
@@ -1502,6 +1501,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
- shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000000 SP_FS_OBJ_START_HI: 0
!+ 00000100 SP_BLEND_CNTL: { UNK8 }
+ 00000000 SP_SRGB_CNTL: { 0 }
!+ 0000000f SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
@@ -1565,12 +1565,12 @@ t4 write RB_BLIT_INFO (88e3)
t4 write RB_BLIT_DST_INFO (88d7)
RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
RB_BLIT_DST: 0x1013000
RB_BLIT_DST+0x1: 0
RB_BLIT_DST_HI: 0
RB_BLIT_DST_PITCH: 1024
000000000115c03c: 0000: 4888d704 00001807 01013000 00000000 00000010
t4 write RB_BLIT_FLAG_DST (88dc)
RB_BLIT_FLAG_DST: 0x1012000
RB_BLIT_FLAG_DST+0x1: 0
RB_BLIT_FLAG_DST_HI: 0
RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
000000000115c050: 0000: 4088dc83 01012000 00000000 00004001
t4 write RB_BLIT_BASE_GMEM (88d6)
@@ -1588,10 +1588,10 @@ t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
+ 00000000 RB_BLIT_BASE_GMEM: 0
+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
+ 01013000 RB_BLIT_DST: 0x1013000
+ 00000000 RB_BLIT_DST+0x1: 0
+ 00000000 RB_BLIT_DST_HI: 0
+ 00000010 RB_BLIT_DST_PITCH: 1024
+ 01012000 RB_BLIT_FLAG_DST: 0x1012000
+ 00000000 RB_BLIT_FLAG_DST+0x1: 0
+ 00000000 RB_BLIT_FLAG_DST_HI: 0
+ 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
!+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 }
000000000115c068: 0000: 70460001 0000001e
src/freedreno/.gitlab-ci/reference/fd-clouds.log
+46 -46
View File
@@ -252,18 +252,18 @@ t4 write RB_DEPTH_BUFFER_INFO (8872)
RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
RB_DEPTH_BUFFER_PITCH: 0
RB_DEPTH_BUFFER_ARRAY_PITCH: 0
RB_DEPTH_BUFFER_BASE_LO: 0
RB_DEPTH_BUFFER_BASE: 0
RB_DEPTH_BUFFER_BASE_HI: 0
RB_DEPTH_BUFFER_BASE_GMEM: 0
0000000001d91284: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000
t4 write GRAS_SU_DEPTH_BUFFER_INFO (8098)
GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
0000000001d912a0: 0000: 48809801 00000000
t4 write GRAS_LRZ_BUFFER_BASE_LO (8103)
GRAS_LRZ_BUFFER_BASE_LO: 0
t4 write GRAS_LRZ_BUFFER_BASE (8103)
GRAS_LRZ_BUFFER_BASE: 0
GRAS_LRZ_BUFFER_BASE_HI: 0
GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
0000000001d912a8: 0000: 48810385 00000000 00000000 00000000 00000000 00000000
t4 write RB_STENCIL_INFO (8881)
@@ -273,15 +273,15 @@ t4 write RB_MRT[0].BUF_INFO (8822)
RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WXYZ }
RB_MRT[0].PITCH: 8704
RB_MRT[0].ARRAY_PITCH: 12533760
RB_MRT[0].BASE_LO: 0x1125000
RB_MRT[0].BASE: 0x1125000
RB_MRT[0].BASE_HI: 0
RB_MRT[0].BASE_GMEM: 0
0000000001d912c8: 0000: 48882286 00002031 00000088 0002fd00 01125000 00000000 00000000
t4 write SP_FS_MRT[0].REG (a996)
SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
0000000001d912e4: 0000: 48a99601 00000031
t4 write RB_MRT_FLAG_BUFFER[0].ADDR_LO (8903)
RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0
t4 write RB_MRT_FLAG_BUFFER[0].ADDR (8903)
RB_MRT_FLAG_BUFFER[0].ADDR: 0
RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
0000000001d912ec: 0000: 40890383 00000000 00000000 00000000
@@ -365,7 +365,7 @@ t4 write VFD_MODE_CNTL (a007)
0000000001d913cc: 0000: 40a00701 00000001
t4 write VSC_BIN_SIZE (0c02)
VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 }
VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x1d65800
VSC_DRAW_STRM_SIZE_ADDRESS: 0x1d65800
VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
0000000001d913d4: 0000: 400c0283 00001e11 01d65800 00000000
t4 write VSC_BIN_COUNT (0c06)
@@ -407,14 +407,14 @@ t4 write VSC_PIPE_CONFIG[0].REG (0c10)
0000000001d913ec: 0000: 400c1020 04100000 04100001 04100002 04100003 04100400 04100401 04100402
0000000001d9140c: 0020: 04100403 04100800 04100801 04100802 04100803 00000000 00000000 00000000
*
t4 write VSC_PRIM_STRM_ADDRESS_LO (0c30)
VSC_PRIM_STRM_ADDRESS_LO: 0x1d67000
t4 write VSC_PRIM_STRM_ADDRESS (0c30)
VSC_PRIM_STRM_ADDRESS: 0x1d67000
VSC_PRIM_STRM_ADDRESS_HI: 0
VSC_PRIM_STRM_PITCH: 0x1040
VSC_PRIM_STRM_LIMIT: 0x28000
0000000001d91470: 0000: 480c3004 01d67000 00000000 00001040 00028000
t4 write VSC_DRAW_STRM_ADDRESS_LO (0c34)
VSC_DRAW_STRM_ADDRESS_LO: 0x1d5d000
t4 write VSC_DRAW_STRM_ADDRESS (0c34)
VSC_DRAW_STRM_ADDRESS: 0x1d5d000
VSC_DRAW_STRM_ADDRESS_HI: 0
VSC_DRAW_STRM_PITCH: 0x440
VSC_DRAW_STRM_LIMIT: 0xa000
@@ -624,9 +624,8 @@ t4 write SP_VS_CTRL_REG0 (a800)
t4 write SP_VS_INSTRLEN (a824)
SP_VS_INSTRLEN: 1
0000000001121030: 0000: 40a82401 00000001
t4 write SP_VS_OBJ_START_LO (a81c)
SP_VS_OBJ_START_LO: 0x1011000 base=1011000, offset=0, size=128
SP_VS_OBJ_START_HI: 0 base=1011000, offset=0, size=128
t4 write SP_VS_OBJ_START (a81c)
SP_VS_OBJ_START: 0x1011000 base=1011000, offset=0, size=128
0000000001011000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
:0:0000:0000[03000000x_00000000x] end
@@ -639,6 +638,7 @@ t4 write SP_VS_OBJ_START_LO (a81c)
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
SP_VS_OBJ_START_HI: 0
0000000001121038: 0000: 48a81c02 01011000 00000000
t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
@@ -780,7 +780,7 @@ t4 write GRAS_SU_DEPTH_PLANE_CNTL (8094)
0000000001116020: 0020: 40a0d001 0000000f 48a00001 00000101
t4 write VFD_FETCH[0].BASE (a010)
VFD_FETCH[0].BASE: 0x1016000
VFD_FETCH[0].BASE+0x1: 0
VFD_FETCH[0].BASE_HI: 0
VFD_FETCH[0].SIZE: 1048576
VFD_FETCH[0].STRIDE: 12
0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c
@@ -875,7 +875,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 00000002 CP_SCRATCH[0x7].REG: 2
:0,1,11,2
!+ 00001e11 VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 }
!+ 01d65800 VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x1d65800
!+ 01d65800 VSC_DRAW_STRM_SIZE_ADDRESS: 0x1d65800
+ 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
!+ 00001808 VSC_BIN_COUNT: { NX = 4 | NY = 3 }
!+ 04100000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 }
@@ -910,11 +910,11 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 VSC_PIPE_CONFIG[0x1d].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
+ 00000000 VSC_PIPE_CONFIG[0x1e].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
+ 00000000 VSC_PIPE_CONFIG[0x1f].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
!+ 01d67000 VSC_PRIM_STRM_ADDRESS_LO: 0x1d67000
!+ 01d67000 VSC_PRIM_STRM_ADDRESS: 0x1d67000
+ 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0
!+ 00001040 VSC_PRIM_STRM_PITCH: 0x1040
!+ 00028000 VSC_PRIM_STRM_LIMIT: 0x28000
!+ 01d5d000 VSC_DRAW_STRM_ADDRESS_LO: 0x1d5d000
!+ 01d5d000 VSC_DRAW_STRM_ADDRESS: 0x1d5d000
+ 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0
!+ 00000440 VSC_DRAW_STRM_PITCH: 0x440
!+ 0000a000 VSC_DRAW_STRM_LIMIT: 0xa000
@@ -957,10 +957,10 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 059f086f GRAS_SC_WINDOW_SCISSOR_BR: { X = 2159 | Y = 1439 }
+ 00000000 GRAS_LRZ_CNTL: { 0 }
+ 00000000 GRAS_UNKNOWN_8101: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
+ 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
+ 00000000 GRAS_SAMPLE_CNTL: { 0 }
!+ 00000002 GRAS_UNKNOWN_8110: 0x2
@@ -990,7 +990,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 00002031 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WXYZ }
!+ 00000088 RB_MRT[0].PITCH: 8704
!+ 0002fd00 RB_MRT[0].ARRAY_PITCH: 12533760
!+ 01125000 RB_MRT[0].BASE_LO: 0x1125000
!+ 01125000 RB_MRT[0].BASE: 0x1125000
+ 00000000 RB_MRT[0].BASE_HI: 0
+ 00000000 RB_MRT[0].BASE_GMEM: 0
+ 00000000 RB_BLEND_RED_F32: 0.000000
@@ -1004,7 +1004,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
+ 00000000 RB_DEPTH_BUFFER_PITCH: 0
+ 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_LO: 0
+ 00000000 RB_DEPTH_BUFFER_BASE: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_HI: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0
+ 00000000 RB_Z_BOUNDS_MIN: 0.000000
@@ -1019,7 +1019,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 00001e11 RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
+ 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000000 RB_UNKNOWN_88F0: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
!+ 00000001 RB_UNKNOWN_8E01: 0x1
@@ -1069,7 +1069,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 VFD_INDEX_OFFSET: 0
+ 00000000 VFD_INSTANCE_START_OFFSET: 0
!+ 01016000 VFD_FETCH[0].BASE: 0x1016000
+ 00000000 VFD_FETCH[0].BASE+0x1: 0
+ 00000000 VFD_FETCH[0].BASE_HI: 0
!+ 00100000 VFD_FETCH[0].SIZE: 1048576
!+ 0000000c VFD_FETCH[0].STRIDE: 12
!+ c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
@@ -1081,8 +1081,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 00000f00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
+ 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
+ 00000000 SP_VS_OBJ_FIRST_EXEC_OFFSET: 0
!+ 01011000 SP_VS_OBJ_START_LO: 0x1011000 base=1011000, offset=0, size=128
+ 00000000 SP_VS_OBJ_START_HI: 0 base=1011000, offset=0, size=128
!+ 01011000 SP_VS_OBJ_START: 0x1011000 base=1011000, offset=0, size=128
0000000001011000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
:0:0000:0000[03000000x_00000000x] end
@@ -1095,6 +1094,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000000 SP_VS_OBJ_START_HI: 0
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
@@ -1918,9 +1918,8 @@ t4 write SP_VS_CTRL_REG0 (a800)
t4 write SP_VS_INSTRLEN (a824)
SP_VS_INSTRLEN: 1
0000000001120030: 0000: 40a82401 00000001
t4 write SP_VS_OBJ_START_LO (a81c)
SP_VS_OBJ_START_LO: 0x1012000 base=1012000, offset=0, size=128
SP_VS_OBJ_START_HI: 0 base=1012000, offset=0, size=128
t4 write SP_VS_OBJ_START (a81c)
SP_VS_OBJ_START: 0x1012000 base=1012000, offset=0, size=128
0000000001012000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
:0:0000:0000[03000000x_00000000x] end
@@ -1933,6 +1932,7 @@ t4 write SP_VS_OBJ_START_LO (a81c)
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
SP_VS_OBJ_START_HI: 0
0000000001120038: 0000: 48a81c02 01012000 00000000
t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
@@ -2040,9 +2040,8 @@ t4 write VPC_UNKNOWN_9107 (9107)
t4 write SP_FS_INSTRLEN (ab05)
SP_FS_INSTRLEN: 88
0000000001120150: 0000: 40ab0501 00000058
t4 write SP_FS_OBJ_START_LO (a983)
SP_FS_OBJ_START_LO: 0x1013000 base=1013000, offset=0, size=11264
SP_FS_OBJ_START_HI: 0 base=1013000, offset=0, size=11264
t4 write SP_FS_OBJ_START (a983)
SP_FS_OBJ_START: 0x1013000 base=1013000, offset=0, size=11264
0000000001013000: 0000: 40400000 204cc000 00000000 204cc006 3e99999a 204cc004 20080014 42700008
0000000001013020: 0020: 10331003 6380000c 00000006 200cc00d 00041003 40700004 00000000 20244014
0000000001013040: 0040: 1036000c 4070000e 0000000d 200cc005 1034000c 4070000f 10251024 63820004
@@ -3465,6 +3464,7 @@ t4 write SP_FS_OBJ_START_LO (a983)
- shaderdb: 0 last-baryf, 0 half, 19 full, 29 constlen
- shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 1326 sstall, 140 (ss), 0 (sy)
SP_FS_OBJ_START_HI: 0
0000000001120158: 0000: 40a98302 01013000 00000000
t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 88 }
@@ -4995,7 +4995,7 @@ t4 write SP_FS_OUTPUT_CNTL1 (a98d)
0000000001116020: 0020: 40a0d001 0000000f 48a00001 00000101
t4 write VFD_FETCH[0].BASE (a010)
VFD_FETCH[0].BASE: 0x1016000
VFD_FETCH[0].BASE+0x1: 0
VFD_FETCH[0].BASE_HI: 0
VFD_FETCH[0].SIZE: 1048576
VFD_FETCH[0].STRIDE: 12
0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c
@@ -5040,9 +5040,9 @@ t7 opcode: CP_LOAD_STATE6 (36) (4 dwords)
{ EXT_SRC_ADDR = 0x11160a0 }
{ EXT_SRC_ADDR_HI = 0 }
00000000011160a0: 0000: 70b68003 003a0000 011160a0 00000000
t4 write SP_IBO_LO (ab1a)
SP_IBO_LO: 0x11160a0 base=1116000, offset=160, size=388
SP_IBO_HI: 0 base=1116000, offset=160, size=388
t4 write SP_IBO (ab1a)
SP_IBO: 0x11160a0 base=1116000, offset=160, size=388
SP_IBO_HI: 0
00000000011160b0: 0000: 48ab1a02 011160a0 00000000
t4 write SP_IBO_COUNT (ab20)
SP_IBO_COUNT: 0
@@ -5267,7 +5267,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 VFD_INDEX_OFFSET: 0
+ 00000000 VFD_INSTANCE_START_OFFSET: 0
+ 01016000 VFD_FETCH[0].BASE: 0x1016000
+ 00000000 VFD_FETCH[0].BASE+0x1: 0
+ 00000000 VFD_FETCH[0].BASE_HI: 0
+ 00100000 VFD_FETCH[0].SIZE: 1048576
+ 0000000c VFD_FETCH[0].STRIDE: 12
+ c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
@@ -5277,8 +5277,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000001 SP_VS_PRIMITIVE_CNTL: { OUT = 1 }
+ 00000f00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
+ 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
!+ 01012000 SP_VS_OBJ_START_LO: 0x1012000 base=1012000, offset=0, size=128
+ 00000000 SP_VS_OBJ_START_HI: 0 base=1012000, offset=0, size=128
!+ 01012000 SP_VS_OBJ_START: 0x1012000 base=1012000, offset=0, size=128
0000000001012000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
:0:0000:0000[03000000x_00000000x] end
@@ -5291,6 +5290,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000000 SP_VS_OBJ_START_HI: 0
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
@@ -5301,8 +5301,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 81508980 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 19 | BRANCHSTACK = 2 | THREADSIZE = THREAD128 | VARYING | MERGEDREGS | 0x1000000 }
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
!+ 01013000 SP_FS_OBJ_START_LO: 0x1013000 base=1013000, offset=0, size=11264
+ 00000000 SP_FS_OBJ_START_HI: 0 base=1013000, offset=0, size=11264
!+ 01013000 SP_FS_OBJ_START: 0x1013000 base=1013000, offset=0, size=11264
0000000001013000: 0000: 40400000 204cc000 00000000 204cc006 3e99999a 204cc004 20080014 42700008
0000000001013020: 0020: 10331003 6380000c 00000006 200cc00d 00041003 40700004 00000000 20244014
0000000001013040: 0040: 1036000c 4070000e 0000000d 200cc005 1034000c 4070000f 10251024 63820004
@@ -6725,6 +6724,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
- shaderdb: 0 last-baryf, 0 half, 19 full, 29 constlen
- shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 1326 sstall, 140 (ss), 0 (sy)
+ 00000000 SP_FS_OBJ_START_HI: 0
!+ 00000100 SP_BLEND_CNTL: { UNK8 }
+ fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
!+ 00000001 SP_FS_OUTPUT_CNTL1: { MRT = 1 }
@@ -6741,8 +6741,8 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000058 SP_FS_INSTRLEN: 88
!+ 011160a0 SP_IBO_LO: 0x11160a0 base=1116000, offset=160, size=388
+ 00000000 SP_IBO_HI: 0 base=1116000, offset=160, size=388
!+ 011160a0 SP_IBO: 0x11160a0 base=1116000, offset=160, size=388
+ 00000000 SP_IBO_HI: 0
+ 00000000 SP_IBO_COUNT: 0
+ 00000100 HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED }
+ 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 }
@@ -6821,7 +6821,7 @@ t4 write RB_BLIT_INFO (88e3)
t4 write RB_BLIT_DST_INFO (88d7)
RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
RB_BLIT_DST: 0x1125000
RB_BLIT_DST+0x1: 0
RB_BLIT_DST_HI: 0
RB_BLIT_DST_PITCH: 8704
RB_BLIT_DST_ARRAY_PITCH: 12533760
0000000001116144: 0000: 4888d785 000018a0 01125000 00000000 00000088 0002fd00
@@ -6849,7 +6849,7 @@ t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
+ 00000000 RB_BLIT_BASE_GMEM: 0
!+ 000018a0 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
!+ 01125000 RB_BLIT_DST: 0x1125000
+ 00000000 RB_BLIT_DST+0x1: 0
+ 00000000 RB_BLIT_DST_HI: 0
!+ 00000088 RB_BLIT_DST_PITCH: 8704
!+ 0002fd00 RB_BLIT_DST_ARRAY_PITCH: 12533760
!+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 }
src/freedreno/computerator/a6xx.c
+3 -3
View File
@@ -165,13 +165,13 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_1_THREADSIZE(THREAD128));
OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2);
OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
OUT_PKT4(ring, REG_A6XX_SP_CS_INSTRLEN, 1);
OUT_RING(ring, v->instrlen);
OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2);
OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
OUT_RELOC(ring, v->bo, 0, 0, 0);
OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
@@ -291,7 +291,7 @@ cs_ibo_emit(struct fd_ringbuffer *ring, struct fd_submit *submit,
CP_LOAD_STATE6_0_NUM_UNIT(kernel->num_bufs));
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO, 2);
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
src/freedreno/decode/cffdec.c
+46 -38
View File
@@ -393,6 +393,11 @@ reg_dump_gpuaddr_hi(const char *name, uint32_t dword, int level)
dump_gpuaddr(gpuaddr_lo | (((uint64_t)dword) << 32), level);
}
static void
reg_dump_gpuaddr64(const char *name, uint64_t qword, int level)
{
dump_gpuaddr(qword, level);
}
static void
dump_shader(const char *ext, void *buf, int bufsz)
@@ -458,6 +463,12 @@ reg_disasm_gpuaddr_hi(const char *name, uint32_t dword, int level)
disasm_gpuaddr(name, gpuaddr_lo | (((uint64_t)dword) << 32), level);
}
static void
reg_disasm_gpuaddr64(const char *name, uint64_t qword, int level)
{
disasm_gpuaddr(name, qword, level);
}
/* Find the value of the TEX_COUNT register that corresponds to the named
* TEX_SAMP/TEX_CONST reg.
*
@@ -520,10 +531,13 @@ reg_dump_tex_const_hi(const char *name, uint32_t dword, int level)
* Registers with special handling (rnndec_decode() handles rest):
*/
#define REG(x, fxn) { #x, fxn }
#define REG64(x, fxn) { #x, .fxn64 = fxn, .is_reg64 = true }
static struct {
const char *regname;
void (*fxn)(const char *name, uint32_t dword, int level);
void (*fxn64)(const char *name, uint64_t qword, int level);
uint32_t regbase;
bool is_reg64;
} reg_a2xx[] = {
REG(CP_SCRATCH_REG0, reg_dump_scratch),
REG(CP_SCRATCH_REG1, reg_dump_scratch),
@@ -663,43 +677,25 @@ static struct {
REG(CP_SCRATCH[0x6].REG, reg_dump_scratch),
REG(CP_SCRATCH[0x7].REG, reg_dump_scratch),
REG(SP_VS_OBJ_START_LO, reg_gpuaddr_lo),
REG(SP_VS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
REG(SP_HS_OBJ_START_LO, reg_gpuaddr_lo),
REG(SP_HS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
REG(SP_DS_OBJ_START_LO, reg_gpuaddr_lo),
REG(SP_DS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
REG(SP_GS_OBJ_START_LO, reg_gpuaddr_lo),
REG(SP_GS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
REG(SP_FS_OBJ_START_LO, reg_gpuaddr_lo),
REG(SP_FS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
REG(SP_CS_OBJ_START_LO, reg_gpuaddr_lo),
REG(SP_CS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
REG64(SP_VS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_HS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_DS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_GS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_FS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_CS_OBJ_START, reg_disasm_gpuaddr64),
REG(SP_VS_TEX_CONST_LO, reg_gpuaddr_lo),
REG(SP_VS_TEX_CONST_HI, reg_dump_tex_const_hi),
REG(SP_VS_TEX_SAMP_LO, reg_gpuaddr_lo),
REG(SP_VS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
REG(SP_HS_TEX_CONST_LO, reg_gpuaddr_lo),
REG(SP_HS_TEX_CONST_HI, reg_dump_tex_const_hi),
REG(SP_HS_TEX_SAMP_LO, reg_gpuaddr_lo),
REG(SP_HS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
REG(SP_DS_TEX_CONST_LO, reg_gpuaddr_lo),
REG(SP_DS_TEX_CONST_HI, reg_dump_tex_const_hi),
REG(SP_DS_TEX_SAMP_LO, reg_gpuaddr_lo),
REG(SP_DS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
REG(SP_GS_TEX_CONST_LO, reg_gpuaddr_lo),
REG(SP_GS_TEX_CONST_HI, reg_dump_tex_const_hi),
REG(SP_GS_TEX_SAMP_LO, reg_gpuaddr_lo),
REG(SP_GS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
REG(SP_FS_TEX_CONST_LO, reg_gpuaddr_lo),
REG(SP_FS_TEX_CONST_HI, reg_dump_tex_const_hi),
REG(SP_FS_TEX_SAMP_LO, reg_gpuaddr_lo),
REG(SP_FS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
REG(SP_CS_TEX_CONST_LO, reg_gpuaddr_lo),
REG(SP_CS_TEX_CONST_HI, reg_dump_tex_const_hi),
REG(SP_CS_TEX_SAMP_LO, reg_gpuaddr_lo),
REG(SP_CS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
REG64(SP_VS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_VS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_HS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_HS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_DS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_DS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_GS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_GS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_FS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_FS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_CS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_CS_TEX_SAMP, reg_dump_gpuaddr64),
{NULL},
}, *type0_reg;
@@ -826,8 +822,15 @@ dump_register_val(uint32_t regbase, uint32_t dword, int level)
* might be useful for other gen's too, but at least a5xx has
* the _HI/_LO suffix we can look for. Maybe a better approach
* would be some special annotation in the xml..
* for a6xx use "address" and "waddress" types
*
*/
if (options->gpu_id >= 500) {
if (options->gpu_id >= 600) {
if (!strcmp(info->typeinfo->name, "address") ||
!strcmp(info->typeinfo->name, "waddress")) {
gpuaddr = (((uint64_t)reg_val(regbase+1)) << 32) | dword;
}
} else if (options->gpu_id >= 500) {
if (endswith(regbase, "_HI") && endswith(regbase-1, "_LO")) {
gpuaddr = (((uint64_t)dword) << 32) | reg_val(regbase-1);
} else if (endswith(regbase, "_LO") && endswith(regbase+1, "_HI")) {
@@ -866,7 +869,12 @@ dump_register(uint32_t regbase, uint32_t dword, int level)
for (unsigned idx = 0; type0_reg[idx].regname; idx++) {
if (type0_reg[idx].regbase == regbase) {
type0_reg[idx].fxn(type0_reg[idx].regname, dword, level);
if (type0_reg[idx].is_reg64) {
uint64_t qword = (((uint64_t)reg_val(regbase+1)) << 32) | dword;
type0_reg[idx].fxn64(type0_reg[idx].regname, qword, level);
} else {
type0_reg[idx].fxn(type0_reg[idx].regname, dword, level);
}
break;
}
}
src/freedreno/decode/scripts/parse-submits.lua
+18 -19
View File
@@ -212,26 +212,26 @@ function CP_EVENT_WRITE(pkt, size)
-- to avoid relying on RB_BLIT_DST also getting written:
for n = 0,r.RB_FS_OUTPUT_CNTL1.MRT-1 do
if r.RB_MRT[n].BASE_GMEM == r.RB_BLIT_BASE_GMEM then
sysmem = r.RB_MRT[n].BASE_LO | (r.RB_MRT[n].BASE_HI << 32)
flag = r.RB_MRT_FLAG_BUFFER[n].ADDR_LO | (r.RB_MRT_FLAG_BUFFER[n].ADDR_HI << 32)
sysmem = r.RB_MRT[n].BASE
flag = r.RB_MRT_FLAG_BUFFER[n].ADDR
break
end
end
if sysmem == 0 and r.RB_BLIT_BASE_GMEM == r.RB_DEPTH_BUFFER_BASE_GMEM then
sysmem = r.RB_DEPTH_BUFFER_BASE_LO | (r.RB_DEPTH_BUFFER_BASE_HI << 32)
flag = r.RB_DEPTH_FLAG_BUFFER_BASE_LO | (r.RB_DEPTH_FLAG_BUFFER_BASE_HI << 32)
sysmem = r.RB_DEPTH_BUFFER_BASE
flag = r.RB_DEPTH_FLAG_BUFFER_BASE
end
--NOTE this can get confused by previous blits:
--if sysmem == 0 then
-- -- fallback:
-- sysmem = r.RB_BLIT_DST_LO | (r.RB_BLIT_DST_HI << 32)
-- flag = r.RB_BLIT_FLAG_DST_LO | (r.RB_BLIT_FLAG_DST_HI << 32)
-- sysmem = r.RB_BLIT_DST
-- flag = r.RB_BLIT_FLAG_DST
--end
if not r.RB_BLIT_DST_INFO.FLAGS then
flag = 0
end
-- TODO maybe just emit RB_BLIT_DST_LO/HI for clears.. otherwise
-- TODO maybe just emit RB_BLIT_DST/HI for clears.. otherwise
-- we get confused by stale values in registers.. not sure
-- if this is a problem w/ blob
push_mrt(r.RB_BLIT_DST_INFO.COLOR_FORMAT,
@@ -260,7 +260,7 @@ function handle_blit()
-- blob sometimes uses CP_BLIT for resolves, so filter those out:
-- TODO it would be nice to not hard-code GMEM addr:
-- TODO I guess the src can be an offset from GMEM addr..
if r.SP_PS_2D_SRC_LO == 0x100000 and not r.RB_2D_BLIT_CNTL.SOLID_COLOR then
if r.SP_PS_2D_SRC == 0x100000 and not r.RB_2D_BLIT_CNTL.SOLID_COLOR then
resolved[0] = 1
return
end
@@ -276,19 +276,19 @@ function handle_blit()
r.GRAS_2D_DST_BR.X + 1,
r.GRAS_2D_DST_BR.Y + 1,
"MSAA_ONE",
r.RB_2D_DST_LO | (r.RB_2D_DST_HI << 32),
r.RB_2D_DST_FLAGS_LO | (r.RB_2D_DST_FLAGS_HI << 32),
r.RB_2D_DST,
r.RB_2D_DST_FLAGS,
-1)
if r.RB_2D_BLIT_CNTL.SOLID_COLOR then
dbg("CLEAR=%x\n", r.RB_2D_DST_LO | (r.RB_2D_DST_HI << 32))
cleared[r.RB_2D_DST_LO | (r.RB_2D_DST_HI << 32)] = 1
dbg("CLEAR=%x\n", r.RB_2D_DST)
cleared[r.RB_2D_DST] = 1
else
push_source(r.SP_2D_SRC_FORMAT.COLOR_FORMAT,
r.GRAS_2D_SRC_BR_X.X + 1,
r.GRAS_2D_SRC_BR_Y.Y + 1,
"MSAA_ONE",
r.SP_PS_2D_SRC_LO | (r.SP_PS_2D_SRC_HI << 32),
r.SP_PS_2D_SRC_FLAGS_LO | (r.SP_PS_2D_SRC_FLAGS_HI << 32))
r.SP_PS_2D_SRC,
r.SP_PS_2D_SRC_FLAGS)
end
blits = blits + 1
finish()
@@ -364,14 +364,13 @@ function draw(primtype, nindx)
r.GRAS_SC_SCREEN_SCISSOR[0].BR.X + 1,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.Y + 1,
r.RB_MSAA_CNTL.SAMPLES,
r.RB_MRT[n].BASE_LO | (r.RB_MRT[n].BASE_HI << 32),
r.RB_MRT_FLAG_BUFFER[n].ADDR_LO | (r.RB_MRT_FLAG_BUFFER[n].ADDR_HI << 32),
r.RB_MRT[n].BASE,
r.RB_MRT_FLAG_BUFFER[n].ADDR,
r.RB_MRT[n].BASE_GMEM)
end
end
local depthbase = r.RB_DEPTH_BUFFER_BASE_LO |
(r.RB_DEPTH_BUFFER_BASE_HI << 32)
local depthbase = r.RB_DEPTH_BUFFER_BASE
if depthbase ~= 0 then
push_mrt(r.RB_DEPTH_BUFFER_INFO.DEPTH_FORMAT,
@@ -379,7 +378,7 @@ function draw(primtype, nindx)
r.GRAS_SC_SCREEN_SCISSOR[0].BR.Y + 1,
r.RB_MSAA_CNTL.SAMPLES,
depthbase,
r.RB_DEPTH_FLAG_BUFFER_BASE_LO | (r.RB_DEPTH_FLAG_BUFFER_BASE_HI << 32),
r.RB_DEPTH_FLAG_BUFFER_BASE,
r.RB_DEPTH_BUFFER_BASE_GMEM)
end
src/freedreno/registers/adreno/a6xx.xml
+26 -94
View File
@@ -1462,8 +1462,6 @@ to upconvert to 32b float internally?
<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
<bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
</reg32>
<reg32 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS_LO"/>
<reg32 offset="0x0c04" name="VSC_DRAW_STRM_SIZE_ADDRESS_HI"/>
<reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/>
<reg32 offset="0x0c06" name="VSC_BIN_COUNT">
<bitfield name="NX" low="1" high="10" type="uint"/>
@@ -1495,13 +1493,9 @@ to upconvert to 32b float internally?
LIMIT is set to PITCH - 64, to make room for a bit of overflow
-->
<reg32 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS_LO"/>
<reg32 offset="0x0c31" name="VSC_PRIM_STRM_ADDRESS_HI"/>
<reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/>
<reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/>
<reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT"/>
<reg32 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS_LO"/>
<reg32 offset="0x0c35" name="VSC_DRAW_STRM_ADDRESS_HI"/>
<reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/>
<reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/>
<reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT"/>
@@ -1726,8 +1720,6 @@ to upconvert to 32b float internally?
<reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
</reg32>
<reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
<reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
<reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress"/>
<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
<!-- TODO: fix the shr fields -->
@@ -1765,9 +1757,7 @@ to upconvert to 32b float internally?
increases beyond 1 page. Not sure if that is an actual limit or
not.
-->
<reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
<reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
<reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/>
<reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/>
<!-- 0x8108 invalid -->
<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
@@ -2000,9 +1990,6 @@ to upconvert to 32b float internally?
restore for context switch, or just to simplify state setup to
not have to care about GMEM vs BYPASS mode.
-->
<reg32 offset="0x5" name="BASE_LO"/>
<reg32 offset="0x6" name="BASE_HI"/>
<!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
<reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
@@ -2051,8 +2038,6 @@ to upconvert to 32b float internally?
</reg32>
<reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint"/>
<reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint"/>
<reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
<reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
<reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64"/>
<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
@@ -2084,8 +2069,6 @@ to upconvert to 32b float internally?
</reg32>
<reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint"/>
<reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint"/>
<reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
<reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
<reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64"/>
<reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
<reg32 offset="0x8887" name="RB_STENCILREF">
@@ -2141,14 +2124,10 @@ to upconvert to 32b float internally?
<bitfield name="UNK15" pos="15" type="boolean"/>
</reg32>
<reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64"/>
<reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
<reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
<reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
<!-- array-pitch is size of layer -->
<reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
<reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64"/>
<reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
<reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
<reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
@@ -2188,8 +2167,6 @@ to upconvert to 32b float internally?
</reg32>
<reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
<!-- 0x88f5-0x88ff invalid -->
<reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
<reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
<reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64"/>
<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
<bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
@@ -2198,8 +2175,6 @@ to upconvert to 32b float internally?
<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
</reg32>
<array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
<reg32 offset="0" name="ADDR_LO"/>
<reg32 offset="1" name="ADDR_HI"/>
<reg64 offset="0" name="ADDR" type="waddress" align="64"/>
<reg32 offset="2" name="PITCH">
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
@@ -2207,8 +2182,6 @@ to upconvert to 32b float internally?
</reg32>
</array>
<!-- 0x891b-0x8926 invalid -->
<reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
<reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
<reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16"/>
<!-- 0x8929-0x89ff invalid -->
@@ -2234,8 +2207,6 @@ to upconvert to 32b float internally?
<!-- 0x8c02-0x8c16 invalid -->
<!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
<reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
<reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
<reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
<reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64"/>
<reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
<!-- this is a guess but seems likely (for NV12/IYUV): -->
@@ -2243,8 +2214,6 @@ to upconvert to 32b float internally?
<reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint"/>
<reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64"/>
<reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
<reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
<reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64"/>
<reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/>
<!-- this is a guess but seems likely (for NV12 with UBWC): -->
@@ -2398,20 +2367,14 @@ to upconvert to 32b float internally?
<bitfield name="B_EN" pos="23" type="boolean"/>
</reg32>
<reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
<reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
<reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32"/>
<reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32"/>
<array offset="0x921a" name="VPC_SO" stride="7" length="4">
<reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
<reg32 offset="0" name="BUFFER_BASE_LO"/>
<reg32 offset="1" name="BUFFER_BASE_HI"/>
<reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
<reg32 offset="3" name="NCOMP" low="0" high="9"/> <!-- component count -->
<reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
<reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
<reg32 offset="5" name="FLUSH_BASE_LO"/>
<reg32 offset="6" name="FLUSH_BASE_HI"/>
</array>
<reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT">
@@ -2623,9 +2586,7 @@ to upconvert to 32b float internally?
<!-- TODO: 0x9e00-0xa000 range incomplete -->
<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
<reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
<reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
<reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
<!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
<reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
@@ -2690,9 +2651,7 @@ to upconvert to 32b float internally?
<reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
<reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
<array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
<reg64 offset="0x0" name="BASE" type="address"/>
<reg32 offset="0x0" name="BASE_LO"/>
<reg32 offset="0x1" name="BASE_HI"/>
<reg64 offset="0x0" name="BASE" type="address" align="1"/>
<reg32 offset="0x2" name="SIZE" type="uint"/>
<reg32 offset="0x3" name="STRIDE" type="uint"/>
</array>
@@ -2872,8 +2831,7 @@ to upconvert to 32b float internally?
</bitset>
<reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
<reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
<reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
<reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32"/>
<reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
@@ -2892,8 +2850,7 @@ to upconvert to 32b float internally?
<reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint"/>
<reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
<reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
<reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
<reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32"/>
<reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
@@ -2925,8 +2882,7 @@ to upconvert to 32b float internally?
</array>
<reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
<reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
<reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
<reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32"/>
<reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
@@ -2971,8 +2927,7 @@ to upconvert to 32b float internally?
</array>
<reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
<reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
<reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
<reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32"/>
<reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
@@ -2981,22 +2936,14 @@ to upconvert to 32b float internally?
<reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
<reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" low="0" high="18" shr="11"/>
<reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
<reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
<reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
<reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
<reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
<reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
<reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
<reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
<reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
<reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
<reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
<reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
<reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
<reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
<reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
<reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
<reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16"/>
<reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16"/>
<reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16"/>
<reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16"/>
<reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64"/>
<reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64"/>
<reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64"/>
<reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64"/>
<reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
<reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex">
@@ -3007,8 +2954,7 @@ to upconvert to 32b float internally?
</reg32>
<reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
<reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
<reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
<reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32"/>
<reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
@@ -3113,15 +3059,6 @@ to upconvert to 32b float internally?
<reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
<reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
<reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
<reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
<reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
<reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
<reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
<reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
<reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
<reg64 offset="0" name="ADDR" type="waddress"/>
</array>
@@ -3136,8 +3073,7 @@ to upconvert to 32b float internally?
<reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
<reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
<reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
<reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
<reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32"/>
<reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
@@ -3153,11 +3089,14 @@ to upconvert to 32b float internally?
</doc>
</reg32>
<reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16"/>
<reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16"/>
<reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64"/>
<reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64"/>
<!--
IBO state for compute shader:
-->
<reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
<reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
<reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>
<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
<!-- always 0x5 ? -->
@@ -3184,8 +3123,7 @@ to upconvert to 32b float internally?
Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders.
-->
<reg32 offset="0xab1a" name="SP_IBO_LO"/>
<reg32 offset="0xab1b" name="SP_IBO_HI"/>
<reg64 offset="0xab1a" name="SP_IBO" type="address" align="16"/>
<reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
<reg32 offset="0xacc0" name="SP_2D_DST_FORMAT">
@@ -3224,7 +3162,7 @@ to upconvert to 32b float internally?
"a6xx_sp_ps_tp_cluster" but this actually specifies the border
color base for compute shaders.
-->
<reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
<reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128"/>
<!-- always 0x0 ? -->
<reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
<reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
@@ -3240,9 +3178,7 @@ to upconvert to 32b float internally?
</reg32>
<!-- looks to work in the same way as a5xx: -->
<reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
<reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
<reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
<reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128"/>
<reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
<reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
<reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
@@ -3259,15 +3195,11 @@ to upconvert to 32b float internally?
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
</reg32>
<reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
<reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
<reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="waddress"/>
<reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
<bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
</reg32>
<reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
<reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
<reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="waddress"/>
<reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
src/freedreno/registers/gen_header.py
+4 -4
View File
@@ -109,7 +109,7 @@ class Bitset(object):
else:
self.fields = []
def dump_pack_struct(self, prefix=None, array=None):
def dump_pack_struct(self, prefix=None, array=None, bit_size=32):
def field_name(prefix, name):
if f.name:
name = f.name.lower()
@@ -129,11 +129,11 @@ class Bitset(object):
value_name = "dword"
print("struct %s {" % prefix)
for f in self.fields:
if f.type == "waddress":
value_name = "qword"
if f.type in [ "address", "waddress" ]:
tab_to(" __bo_type", "bo;")
tab_to(" uint32_t", "bo_offset;")
if bit_size == 64:
value_name = "qword"
continue
name = field_name(prefix, f.name)
@@ -276,7 +276,7 @@ class Reg(object):
def dump_pack_struct(self):
if self.bitset.inline:
self.bitset.dump_pack_struct(self.full_name, not self.array == None)
self.bitset.dump_pack_struct(self.full_name, not self.array == None, self.bit_size)
def parse_variants(attrs):
src/freedreno/rnn/rnndec.c
+8 -1
View File
@@ -397,7 +397,14 @@ static struct rnndecaddrinfo *trymatch (struct rnndeccontext *ctx, struct rnndel
if (elems[i]->length != 1)
res->name = appendidx(ctx, res->name, idx, elems[i]->index);
if (offset) {
asprintf (&tmp, "%s+%s%#"PRIx64"%s", res->name, ctx->colors->err, offset, ctx->colors->reset);
/* use _HI suffix for addresses */
if (offset == 1 &&
(!strcmp(res->typeinfo->name, "address") ||
!strcmp(res->typeinfo->name, "waddress"))) {
asprintf (&tmp, "%s_HI", res->name);
} else {
asprintf (&tmp, "%s+%s%#"PRIx64"%s", res->name, ctx->colors->err, offset, ctx->colors->reset);
}
free(res->name);
res->name = tmp;
}
src/freedreno/vulkan/tu_clear_blit.c
+9 -16
View File
@@ -152,7 +152,7 @@ r2d_src(struct tu_cmd_buffer *cmd,
tu_cs_emit(cs, iview->SP_PS_2D_SRC_SIZE);
tu_cs_image_ref_2d(cs, iview, layer, true);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 3);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_FLAGS, 3);
tu_cs_image_flag_ref(cs, iview, layer);
}
@@ -188,8 +188,7 @@ r2d_src_buffer(struct tu_cmd_buffer *cmd,
.unk20 = 1,
.unk22 = 1),
A6XX_SP_PS_2D_SRC_SIZE(.width = width, .height = height),
A6XX_SP_PS_2D_SRC_LO((uint32_t) va),
A6XX_SP_PS_2D_SRC_HI(va >> 32),
A6XX_SP_PS_2D_SRC(.qword = va),
A6XX_SP_PS_2D_SRC_PITCH(.pitch = pitch));
}
@@ -200,7 +199,7 @@ r2d_dst(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
tu_cs_emit(cs, iview->RB_2D_DST_INFO);
tu_cs_image_ref_2d(cs, iview, layer, false);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_FLAGS_LO, 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_FLAGS, 3);
tu_cs_image_flag_ref(cs, iview, layer);
}
@@ -223,8 +222,7 @@ r2d_dst_buffer(struct tu_cs *cs, VkFormat vk_format, uint64_t va, uint32_t pitch
.color_format = format.fmt,
.color_swap = format.swap,
.srgb = vk_format_is_srgb(vk_format)),
A6XX_RB_2D_DST_LO((uint32_t) va),
A6XX_RB_2D_DST_HI(va >> 32),
A6XX_RB_2D_DST(.qword = va),
A6XX_RB_2D_DST_PITCH(pitch));
}
@@ -657,8 +655,7 @@ r3d_src_common(struct tu_cmd_buffer *cmd,
CP_LOAD_STATE6_0_NUM_UNIT(1));
tu_cs_emit_qw(cs, texture.iova + A6XX_TEX_CONST_DWORDS * 4);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_TEX_SAMP_LO, 2);
tu_cs_emit_qw(cs, texture.iova + A6XX_TEX_CONST_DWORDS * 4);
tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_SAMP(.qword = texture.iova + A6XX_TEX_CONST_DWORDS * 4));
tu_cs_emit_pkt7(cs, CP_LOAD_STATE6_FRAG, 3);
tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
@@ -668,9 +665,7 @@ r3d_src_common(struct tu_cmd_buffer *cmd,
CP_LOAD_STATE6_0_NUM_UNIT(1));
tu_cs_emit_qw(cs, texture.iova);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_TEX_CONST_LO, 2);
tu_cs_emit_qw(cs, texture.iova);
tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_COUNT(1));
}
@@ -760,8 +755,7 @@ r3d_dst_buffer(struct tu_cs *cs, VkFormat vk_format, uint64_t va, uint32_t pitch
A6XX_RB_MRT_BUF_INFO(0, .color_format = format.fmt, .color_swap = format.swap),
A6XX_RB_MRT_PITCH(0, pitch),
A6XX_RB_MRT_ARRAY_PITCH(0, 0),
A6XX_RB_MRT_BASE_LO(0, (uint32_t) va),
A6XX_RB_MRT_BASE_HI(0, va >> 32),
A6XX_RB_MRT_BASE(0, .qword = va),
A6XX_RB_MRT_BASE_GMEM(0, 0));
tu_cs_emit_regs(cs, A6XX_RB_RENDER_CNTL());
@@ -2407,7 +2401,7 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
tu_cs_emit(cs, iview->RB_BLIT_DST_INFO);
tu_cs_image_ref_2d(cs, iview, 0, false);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
tu_cs_image_flag_ref(cs, iview, 0);
tu_cs_emit_regs(cs,
@@ -2499,8 +2493,7 @@ store_cp_blit(struct tu_cmd_buffer *cmd,
.unk22 = 1),
/* note: src size does not matter when not scaling */
A6XX_SP_PS_2D_SRC_SIZE( .width = 0x3fff, .height = 0x3fff),
A6XX_SP_PS_2D_SRC_LO(cmd->device->physical_device->gmem_base + gmem_offset),
A6XX_SP_PS_2D_SRC_HI(),
A6XX_SP_PS_2D_SRC(.qword = cmd->device->physical_device->gmem_base + gmem_offset),
A6XX_SP_PS_2D_SRC_PITCH(.pitch = cmd->state.framebuffer->tile0.width * cpp));
/* sync GMEM writes with CACHE. */
src/freedreno/vulkan/tu_cmd_buffer.c
+6 -10
View File
@@ -209,14 +209,13 @@ tu6_emit_zs(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs,
A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE, 3);
tu_cs_image_flag_ref(cs, iview, 0);
tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_BUFFER_BASE(.bo = iview->image->bo,
.bo_offset = iview->image->bo_offset + iview->image->lrz_offset),
A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = iview->image->lrz_pitch),
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE());
if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
attachment->format == VK_FORMAT_S8_UINT) {
@@ -258,7 +257,7 @@ tu6_emit_mrt(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs,
A6XX_SP_FS_MRT_REG(i, .dword = iview->SP_FS_MRT_REG));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i), 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(i), 3);
tu_cs_image_flag_ref(cs, iview, 0);
}
@@ -1104,8 +1103,7 @@ tu_emit_input_attachments(struct tu_cmd_buffer *cmd,
CP_LOAD_STATE6_0_NUM_UNIT(subpass->input_count * 2));
tu_cs_emit_qw(&cs, texture.iova);
tu_cs_emit_pkt4(&cs, REG_A6XX_SP_FS_TEX_CONST_LO, 2);
tu_cs_emit_qw(&cs, texture.iova);
tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_COUNT(subpass->input_count * 2));
@@ -1604,8 +1602,7 @@ tu_CmdBindVertexBuffers2EXT(VkCommandBuffer commandBuffer,
for (uint32_t i = 0; i < MAX_VBS; i++) {
tu_cs_emit_regs(&cs,
A6XX_VFD_FETCH_BASE_LO(i, cmd->state.vb[i].base),
A6XX_VFD_FETCH_BASE_HI(i, cmd->state.vb[i].base >> 32),
A6XX_VFD_FETCH_BASE(i, .qword = cmd->state.vb[i].base),
A6XX_VFD_FETCH_SIZE(i, cmd->state.vb[i].size));
}
@@ -3355,8 +3352,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
*/
tu_cs_emit_wfi(cs);
tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
tu_cs_emit_qw(cs, tess_factor_iova);
tu_cs_emit_regs(cs, A6XX_PC_TESSFACTOR_ADDR(.qword = tess_factor_iova));
tu_cs_emit_pkt7(cs, CP_SET_SUBDRAW_SIZE, 1);
tu_cs_emit(cs, draw_count);
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
+2 -2
View File
@@ -562,7 +562,7 @@ emit_blit_dst(struct fd_ringbuffer *ring, struct pipe_resource *prsc, enum pipe_
OUT_RING(ring, 0x00000000);
if (ubwc_enabled) {
OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6);
OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS, 6);
fd6_emit_flag_reference(ring, dst, level, layer);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
@@ -614,7 +614,7 @@ emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info, uns
OUT_RING(ring, 0x00000000);
if (subwc_enabled) {
OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6);
OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS, 6);
fd6_emit_flag_reference(ring, src, info->src.level, layer);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
src/gallium/drivers/freedreno/a6xx/fd6_compute.c
+1 -1
View File
@@ -92,7 +92,7 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_1_THREADSIZE(THREAD128));
OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2);
OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
if (v->instrlen > 0)
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+17 -17
View File
@@ -237,7 +237,7 @@ emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
&entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR, 2);
OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
u_upload_unmap(fd6_ctx->border_color_uploader);
@@ -296,43 +296,43 @@ fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
case PIPE_SHADER_VERTEX:
sb = SB6_VS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_VS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
break;
case PIPE_SHADER_TESS_CTRL:
sb = SB6_HS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP_LO;
tex_const_reg = REG_A6XX_SP_HS_TEX_CONST_LO;
tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_HS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_HS_TEX_COUNT;
break;
case PIPE_SHADER_TESS_EVAL:
sb = SB6_DS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP_LO;
tex_const_reg = REG_A6XX_SP_DS_TEX_CONST_LO;
tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_DS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_DS_TEX_COUNT;
break;
case PIPE_SHADER_GEOMETRY:
sb = SB6_GS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP_LO;
tex_const_reg = REG_A6XX_SP_GS_TEX_CONST_LO;
tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_GS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_GS_TEX_COUNT;
break;
case PIPE_SHADER_FRAGMENT:
sb = SB6_FS_TEX;
opcode = CP_LOAD_STATE6_FRAG;
tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_FS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
break;
case PIPE_SHADER_COMPUTE:
sb = SB6_CS_TEX;
opcode = CP_LOAD_STATE6_FRAG;
tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_CS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
break;
default:
@@ -748,7 +748,7 @@ fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit,
target->stride = info->stride[i];
OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE(i), 3);
/* VPC_SO[i].BUFFER_BASE_LO: */
OUT_RELOC(ring, fd_resource(target->base.buffer)->bo, 0, 0, 0);
OUT_RING(ring, target->base.buffer_size + target->base.buffer_offset);
@@ -773,7 +773,7 @@ fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit,
}
// After a draw HW would write the new offset to offset_bo
OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(i), 2);
OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE(i), 2);
OUT_RELOC(ring, offset_bo, 0, 0, 0);
so->reset &= ~(1 << i);
@@ -1086,7 +1086,7 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(fs)));
OUT_RB(obj, state);
OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
OUT_PKT4(obj, REG_A6XX_SP_IBO, 2);
OUT_RB(obj, state);
/* TODO if we used CP_SET_DRAW_STATE for compute shaders, we could
@@ -1176,7 +1176,7 @@ fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(cp)));
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO, 2);
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+6 -7
View File
@@ -166,7 +166,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE, 3);
fd6_emit_flag_reference(ring, rsc,
zsbuf->u.tex.level, zsbuf->u.tex.first_layer);
@@ -175,10 +175,9 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
A6XX_GRAS_LRZ_BUFFER_BASE(.bo = rsc->lrz),
A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = rsc->lrz_pitch),
// XXX a6xx seems to use a different buffer here.. not sure what for..
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE());
} else {
OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE, 5);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
@@ -217,7 +216,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE, 5);
OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
@@ -877,7 +876,7 @@ emit_blit(struct fd_batch *batch,
OUT_REG(ring, A6XX_RB_BLIT_BASE_GMEM(.dword = base));
if (ubwc_enabled) {
OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST, 3);
fd6_emit_flag_reference(ring, rsc,
psurf->u.tex.level, psurf->u.tex.first_layer);
}
@@ -1403,7 +1402,7 @@ setup_tess_buffers(struct fd_batch *batch, struct fd_ringbuffer *ring)
batch->tessparam_size,
DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR, 2);
OUT_RELOC(ring, batch->tessfactor_bo, 0, 0, 0);
batch->tess_addrs_constobj->cur = batch->tess_addrs_constobj->start;
src/gallium/drivers/freedreno/a6xx/fd6_query.c
+4 -4
View File
@@ -67,7 +67,7 @@ occlusion_resume(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_CONTROL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO, 2);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR, 2);
OUT_RELOC(ring, query_sample(aq, start));
fd6_event_write(batch, ring, ZPASS_DONE, false);
@@ -91,7 +91,7 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch)
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_CONTROL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO, 2);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR, 2);
OUT_RELOC(ring, query_sample(aq, stop));
fd6_event_write(batch, ring, ZPASS_DONE, false);
@@ -399,7 +399,7 @@ primitives_emitted_resume(struct fd_acc_query *aq, struct fd_batch *batch)
struct fd_ringbuffer *ring = batch->draw;
fd_wfi(batch, ring);
OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_COUNTS_LO, 2);
OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_COUNTS, 2);
primitives_relocw(ring, aq, start[0]);
fd6_event_write(batch, ring, WRITE_PRIMITIVE_COUNTS, false);
@@ -413,7 +413,7 @@ primitives_emitted_pause(struct fd_acc_query *aq, struct fd_batch *batch)
fd_wfi(batch, ring);
OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_COUNTS_LO, 2);
OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_COUNTS, 2);
primitives_relocw(ring, aq, stop[0]);
fd6_event_write(batch, ring, WRITE_PRIMITIVE_COUNTS, false);