asahi: Fix depth/stencil buffers

There are a bunch of bits we need to set right to get depth/stencil
loads/stores working, including with independent settings for each. The
kernel "helps" us here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
This commit is contained in:
Alyssa Rosenzweig
2022-05-15 13:22:08 -04:00
committed by Marge Bot
parent 7cb21eb595
commit b891d60efa
4 changed files with 30 additions and 8 deletions
+2 -2
View File
@@ -676,8 +676,8 @@
<field name="Depth clear value" start="0:0" size="32" type="hex"/>
<field name="Stencil clear value" start="1:0" size="8" type="uint"/>
<field name="Unk 1" start="1:8" size="8" type="hex" default="3"/>
<field name="Set when reloading Z 1" start="3:8" size="1" type="bool"/>
<field name="Set when reloading Z 2" start="4:24" size="1" type="bool"/>
<field name="Set when reloading Z or S 1" start="3:8" size="1" type="bool"/>
<field name="Set when reloading Z or S 2" start="4:24" size="1" type="bool"/>
<field name="Z16 Unorm attachment" start="5:8" size="1" type="bool"/>
<field name="Unk 3" start="6:0" size="32" type="hex" default="0xffffffff"/>
<field name="Unk 4" start="7:0" size="32" type="hex" default="0xffffffff"/>
+1
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@@ -542,6 +542,7 @@ agx_flush(struct pipe_context *pctx,
pipeline_reload,
pipeline_store,
clear_pipeline_textures,
ctx->batch->clear,
ctx->batch->clear_depth,
ctx->batch->clear_stencil);
+26 -6
View File
@@ -167,9 +167,13 @@ demo_cmdbuf(uint64_t *buf, size_t size,
uint32_t pipeline_load,
uint32_t pipeline_store,
bool clear_pipeline_textures,
unsigned clear_buffers,
double clear_depth,
unsigned clear_stencil)
{
bool should_clear_depth = clear_buffers & PIPE_CLEAR_DEPTH;
bool should_clear_stencil = clear_buffers & PIPE_CLEAR_STENCIL;
uint32_t *map = (uint32_t *) buf;
memset(map, 0, 518 * 4);
@@ -197,25 +201,31 @@ demo_cmdbuf(uint64_t *buf, size_t size,
const struct util_format_description *desc =
util_format_description(zsbuf->texture->format);
// note: setting 0x4 bit here breaks partial render with depth
cfg.depth_flags = 0x80000; // no compression, clear
cfg.depth_width = framebuffer->width;
cfg.depth_height = framebuffer->height;
if (util_format_has_depth(desc)) {
depth_buffer = agx_map_surface(zsbuf);
cfg.depth_reload = !should_clear_depth;
cfg.depth_flags |= 0x80000;
if (!should_clear_depth) cfg.depth_flags |= 0x8000;
} else {
stencil_buffer = agx_map_surface(zsbuf);
cfg.depth_flags |= 0x40000;
if (!should_clear_stencil) cfg.depth_flags |= 0x4000;
}
if (agx_resource(zsbuf->texture)->separate_stencil) {
stencil_buffer = agx_map_surface_resource(zsbuf,
agx_resource(zsbuf->texture)->separate_stencil);
cfg.depth_flags |= 0x40000;
if (!should_clear_stencil) cfg.depth_flags |= 0x4000;
}
cfg.depth_buffer_if_clearing = depth_buffer;
cfg.stencil_buffer = stencil_buffer;
cfg.stencil_buffer_2 = stencil_buffer;
/* It's unclear how tile size is conveyed for depth/stencil targets,
* which interactions with mipmapping (for example of a 33x33
@@ -225,7 +235,7 @@ demo_cmdbuf(uint64_t *buf, size_t size,
unreachable("todo: mapping other levels");
cfg.depth_buffer = depth_buffer;
cfg.depth_buffer_if_clearing = depth_buffer;
cfg.stencil_buffer_2 = stencil_buffer;
}
}
@@ -236,7 +246,17 @@ demo_cmdbuf(uint64_t *buf, size_t size,
}
agx_pack(map + 292, IOGPU_CLEAR_Z_S, cfg) {
cfg.set_when_reloading_z_1 = clear_pipeline_textures;
cfg.set_when_reloading_z_or_s_1 = clear_pipeline_textures;
if (depth_buffer && !should_clear_depth) {
cfg.set_when_reloading_z_or_s_1 = true;
cfg.set_when_reloading_z_or_s_2 = true;
}
if (stencil_buffer && !should_clear_stencil) {
cfg.set_when_reloading_z_or_s_1 = true;
cfg.set_when_reloading_z_or_s_2 = true;
}
cfg.depth_clear_value = fui(clear_depth);
cfg.stencil_clear_value = clear_stencil & 0xff;
+1
View File
@@ -36,6 +36,7 @@ demo_cmdbuf(uint64_t *buf, size_t size,
uint32_t pipeline_load,
uint32_t pipeline_store,
bool clear_pipeline_textures,
unsigned clear_buffers,
double clear_depth,
unsigned clear_stencil);