asahi: Fix depth/stencil buffers
There are a bunch of bits we need to set right to get depth/stencil loads/stores working, including with independent settings for each. The kernel "helps" us here. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
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@@ -676,8 +676,8 @@
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<field name="Depth clear value" start="0:0" size="32" type="hex"/>
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<field name="Stencil clear value" start="1:0" size="8" type="uint"/>
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<field name="Unk 1" start="1:8" size="8" type="hex" default="3"/>
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<field name="Set when reloading Z 1" start="3:8" size="1" type="bool"/>
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<field name="Set when reloading Z 2" start="4:24" size="1" type="bool"/>
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<field name="Set when reloading Z or S 1" start="3:8" size="1" type="bool"/>
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<field name="Set when reloading Z or S 2" start="4:24" size="1" type="bool"/>
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<field name="Z16 Unorm attachment" start="5:8" size="1" type="bool"/>
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<field name="Unk 3" start="6:0" size="32" type="hex" default="0xffffffff"/>
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<field name="Unk 4" start="7:0" size="32" type="hex" default="0xffffffff"/>
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@@ -542,6 +542,7 @@ agx_flush(struct pipe_context *pctx,
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pipeline_reload,
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pipeline_store,
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clear_pipeline_textures,
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ctx->batch->clear,
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ctx->batch->clear_depth,
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ctx->batch->clear_stencil);
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@@ -167,9 +167,13 @@ demo_cmdbuf(uint64_t *buf, size_t size,
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uint32_t pipeline_load,
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uint32_t pipeline_store,
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bool clear_pipeline_textures,
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unsigned clear_buffers,
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double clear_depth,
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unsigned clear_stencil)
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{
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bool should_clear_depth = clear_buffers & PIPE_CLEAR_DEPTH;
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bool should_clear_stencil = clear_buffers & PIPE_CLEAR_STENCIL;
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uint32_t *map = (uint32_t *) buf;
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memset(map, 0, 518 * 4);
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@@ -197,25 +201,31 @@ demo_cmdbuf(uint64_t *buf, size_t size,
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const struct util_format_description *desc =
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util_format_description(zsbuf->texture->format);
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// note: setting 0x4 bit here breaks partial render with depth
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cfg.depth_flags = 0x80000; // no compression, clear
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cfg.depth_width = framebuffer->width;
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cfg.depth_height = framebuffer->height;
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if (util_format_has_depth(desc)) {
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depth_buffer = agx_map_surface(zsbuf);
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cfg.depth_reload = !should_clear_depth;
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cfg.depth_flags |= 0x80000;
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if (!should_clear_depth) cfg.depth_flags |= 0x8000;
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} else {
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stencil_buffer = agx_map_surface(zsbuf);
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cfg.depth_flags |= 0x40000;
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if (!should_clear_stencil) cfg.depth_flags |= 0x4000;
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}
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if (agx_resource(zsbuf->texture)->separate_stencil) {
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stencil_buffer = agx_map_surface_resource(zsbuf,
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agx_resource(zsbuf->texture)->separate_stencil);
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cfg.depth_flags |= 0x40000;
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if (!should_clear_stencil) cfg.depth_flags |= 0x4000;
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}
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cfg.depth_buffer_if_clearing = depth_buffer;
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cfg.stencil_buffer = stencil_buffer;
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cfg.stencil_buffer_2 = stencil_buffer;
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/* It's unclear how tile size is conveyed for depth/stencil targets,
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* which interactions with mipmapping (for example of a 33x33
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@@ -225,7 +235,7 @@ demo_cmdbuf(uint64_t *buf, size_t size,
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unreachable("todo: mapping other levels");
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cfg.depth_buffer = depth_buffer;
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cfg.depth_buffer_if_clearing = depth_buffer;
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cfg.stencil_buffer_2 = stencil_buffer;
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}
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}
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@@ -236,7 +246,17 @@ demo_cmdbuf(uint64_t *buf, size_t size,
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}
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agx_pack(map + 292, IOGPU_CLEAR_Z_S, cfg) {
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cfg.set_when_reloading_z_1 = clear_pipeline_textures;
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cfg.set_when_reloading_z_or_s_1 = clear_pipeline_textures;
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if (depth_buffer && !should_clear_depth) {
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cfg.set_when_reloading_z_or_s_1 = true;
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cfg.set_when_reloading_z_or_s_2 = true;
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}
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if (stencil_buffer && !should_clear_stencil) {
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cfg.set_when_reloading_z_or_s_1 = true;
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cfg.set_when_reloading_z_or_s_2 = true;
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}
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cfg.depth_clear_value = fui(clear_depth);
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cfg.stencil_clear_value = clear_stencil & 0xff;
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@@ -36,6 +36,7 @@ demo_cmdbuf(uint64_t *buf, size_t size,
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uint32_t pipeline_load,
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uint32_t pipeline_store,
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bool clear_pipeline_textures,
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unsigned clear_buffers,
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double clear_depth,
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unsigned clear_stencil);
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