agx: Use nir_lower_mem_access_bit_sizes
Lowers away 64-bit loads, which we'll create in the sysval lowering for dynamically indexed UBOs/VBOs. The lowering generates pack_64_2x32 instructions, so lower those too. No shader-db changes. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21674>
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@@ -2094,6 +2094,27 @@ agx_fp32_varying_mask(nir_shader *nir)
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return mask;
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}
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static nir_mem_access_size_align
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mem_access_size_align_cb(nir_intrinsic_op intrin, uint8_t bytes, uint32_t align,
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uint32_t align_offset, bool offset_is_const,
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const void *cb_data)
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{
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align = nir_combined_align(align, align_offset);
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assert(util_is_power_of_two_nonzero(align));
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unsigned bit_size = (bytes & 1) ? 8 : (bytes & 2) ? 16 : 32;
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if (align == 2)
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bit_size = MIN2(bit_size, 16);
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else if (align == 1)
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bit_size = 8;
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return (nir_mem_access_size_align){
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.num_components = bytes / (bit_size / 8),
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.bit_size = bit_size,
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.align = bit_size / 8,
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};
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}
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static bool
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agx_should_dump(nir_shader *nir, unsigned agx_dbg_bit)
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{
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@@ -2354,6 +2375,15 @@ agx_compile_shader_nir(nir_shader *nir, struct agx_shader_key *key,
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out->depth_layout = layout;
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}
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/* Late sysval lowering creates large loads. Load lowering creates unpacks */
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NIR_PASS_V(nir, nir_lower_mem_access_bit_sizes,
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nir_var_mem_ssbo | nir_var_mem_constant |
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nir_var_mem_task_payload | nir_var_shader_temp |
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nir_var_function_temp | nir_var_mem_global |
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nir_var_mem_shared,
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mem_access_size_align_cb, NULL);
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NIR_PASS_V(nir, nir_lower_pack);
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/* Late blend lowering creates vectors */
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NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
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NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
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@@ -204,6 +204,7 @@ static const nir_shader_compiler_options agx_nir_options = {
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.lower_fdph = true,
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.lower_ffract = true,
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.lower_pack_half_2x16 = true,
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.lower_pack_64_2x32 = true,
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.lower_unpack_half_2x16 = true,
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.lower_extract_byte = true,
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.lower_insert_byte = true,
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