radv: add a way to disable the HIZ/HiS events based workaround on GFX12

This workaround doesn't mitigate the issue reliably/completely. An
alternative (but complex) solution also exists.

This introduces a small option that allows to disable the current
workaround as preliminary work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36110>

src/amd/vulkan/radv_cmd_buffer.c

@@ -9593,7 +9593,7 @@ radv_gfx12_emit_hiz_his_wa(const struct radv_device *device, const struct radv_c
     * - disable HiZ/HiS completely which is the safest workaround but this is known to decrease performance
     * - emit a dummy BOTTOM_OF_PIPE_TS after every draw which should workaround the hang and maintain performance
     */
-   if (pdev->info.gfx_level == GFX12 && render->has_hiz_his) {
+   if (pdev->use_gfx12_hiz_his_event_wa && render->has_hiz_his) {
       radeon_begin(cs);
       radeon_emit(PKT3(PKT3_RELEASE_MEM, 6, 0));
       radeon_emit(S_490_EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | S_490_EVENT_INDEX(5));

src/amd/vulkan/radv_dgc.c

@@ -286,7 +286,7 @@ radv_get_sequence_size_graphics(const struct radv_indirect_command_layout *layou
       }
    }
 
-   if (pdev->info.gfx_level == GFX12 && pdev->use_hiz) {
+   if (pdev->use_gfx12_hiz_his_event_wa) {
       /* HiZ/HiS hw workaround */
       *cmd_size += 8 * 4;
    }
@@ -1151,7 +1151,7 @@ dgc_gfx12_emit_hiz_his_wa(struct dgc_cmdbuf *cs)
    const struct radv_device *device = cs->dev;
    const struct radv_physical_device *pdev = radv_device_physical(device);
 
-   if (pdev->info.gfx_level == GFX12 && pdev->use_hiz) {
+   if (pdev->use_gfx12_hiz_his_event_wa) {
       dgc_cs_begin(cs);
       dgc_cs_emit_imm(PKT3(PKT3_RELEASE_MEM, 6, 0));
       dgc_cs_emit_imm(S_490_EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | S_490_EVENT_INDEX(5));

src/amd/vulkan/radv_physical_device.c

@@ -2288,6 +2288,9 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm
    if (pdev->info.gfx_level == GFX12 && instance->drirc.disable_hiz_his_gfx12)
       pdev->use_hiz = false;
 
+   pdev->use_gfx12_hiz_his_event_wa =
+      pdev->info.gfx_level == GFX12 && pdev->use_hiz; /* TODO: Implement the alternative solution. */
+
    pdev->use_ngg = (pdev->info.gfx_level >= GFX10 && pdev->info.family != CHIP_NAVI14 &&
                     !(instance->debug_flags & RADV_DEBUG_NO_NGG)) ||
                    pdev->info.gfx_level >= GFX11;

src/amd/vulkan/radv_physical_device.h

@@ -104,6 +104,12 @@ struct radv_physical_device {
    /* Whether to enable HTILE compression for depth/stencil images. */
    bool use_hiz;
 
+   /* Whether the driver uses BOTTOM_OF_PIPE_TS events to workaround random GPU hangs with HiZ/HiS
+    * on GFX12. Note that this workaround doesn't mitigate the issue reliably but it helps in most
+    * scenarios.
+    */
+   bool use_gfx12_hiz_his_event_wa;
+
    /* Whether to enable NGG. */
    bool use_ngg;
 

src/amd/vulkan/radv_queue.c

@@ -705,8 +705,10 @@ radv_emit_ge_rings(struct radv_device *device, struct radeon_cmdbuf *cs, struct
          /* Mitigate the HiZ GPU hang by increasing a timeout when BOTTOM_OF_PIPE_TS is used as the
           * workaround. This must be emitted when the gfx queue is idle.
           */
+         const uint32_t timeout = pdev->use_gfx12_hiz_his_event_wa ? 0xfff : 0;
+
          radeon_emit(PKT3(PKT3_UPDATE_DB_SUMMARIZER_TIMEOUT, 0, 0));
-         radeon_emit(S_EF1_SUMM_CNTL_EVICT_TIMEOUT(0xfff));
+         radeon_emit(S_EF1_SUMM_CNTL_EVICT_TIMEOUT(timeout));
       }
    }