AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radv: align pipeline cache entry and header sizes

Browse Source 
Fixes UBSan error:
../src/amd/vulkan/radv_pipeline_cache.c:603:42: runtime error: member access within misaligned address 0x00000152ebcc for type 'struct cache_entry', which requires 8 byte alignment

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6206>
This commit is contained in:
Rhys Perry
2020-08-06 14:39:04 +01:00
committed by Marge Bot
parent 4f08af6766
commit b50ae77014
1 changed files with 4 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_pipeline_cache.c
+4 -1
View File
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
#include "util/macros.h"
#include "util/mesa-sha1.h"
#include "util/debug.h"
#include "util/disk_cache.h"
@@ -108,6 +109,7 @@ entry_size(struct cache_entry *entry)
for (int i = 0; i < MESA_SHADER_STAGES; ++i)
if (entry->binary_sizes[i])
ret += entry->binary_sizes[i];
ret = align(ret, alignof(struct cache_entry));
return ret;
}
@@ -391,6 +393,7 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device,
for (int i = 0; i < MESA_SHADER_STAGES; ++i)
if (variants[i])
size += binaries[i]->total_size;
size = align(size, alignof(struct cache_entry));
entry = vk_alloc(&cache->alloc, size, 8,
@@ -580,7 +583,7 @@ VkResult radv_GetPipelineCacheData(
}
void *p = pData, *end = pData + *pDataSize;
header = p;
header->header_size = sizeof(*header);
header->header_size = align(sizeof(*header), alignof(struct cache_entry));
header->header_version = VK_PIPELINE_CACHE_HEADER_VERSION_ONE;
header->vendor_id = ATI_VENDOR_ID;
header->device_id = device->physical_device->rad_info.pci_id;