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anv: fix even set/reset on blitter engine

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31928>
This commit is contained in:
Lionel Landwerlin
2024-10-22 09:56:46 +03:00
committed by Marge Bot
parent 423d472a4e
commit b3f487bd0d
1 changed files with 106 additions and 59 deletions
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165
src/intel/vulkan/genX_cmd_buffer.c
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@@ -4191,21 +4191,13 @@ cmd_buffer_has_pending_copy_query(struct anv_cmd_buffer *cmd_buffer)
}
static void
cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
uint32_t n_dep_infos,
const VkDependencyInfo *dep_infos,
const char *reason)
cmd_buffer_accumulate_barrier_bits(struct anv_cmd_buffer *cmd_buffer,
uint32_t n_dep_infos,
const VkDependencyInfo *dep_infos,
VkPipelineStageFlags2 *out_src_stages,
VkPipelineStageFlags2 *out_dst_stages,
enum anv_pipe_bits *out_bits)
{
if (anv_cmd_buffer_is_video_queue(cmd_buffer)) {
cmd_buffer_barrier_video(cmd_buffer, n_dep_infos, dep_infos);
return;
}
if (anv_cmd_buffer_is_blitter_queue(cmd_buffer)) {
cmd_buffer_barrier_blitter(cmd_buffer, n_dep_infos, dep_infos);
return;
}
/* XXX: Right now, we're really dumb and just flush whatever categories
* the app asks for. One of these days we may make this a bit better but
* right now that's all the hardware allows for in most areas.
@@ -4214,6 +4206,7 @@ cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
VkAccessFlags2 dst_flags = 0;
VkPipelineStageFlags2 src_stages = 0;
VkPipelineStageFlags2 dst_stages = 0;
#if GFX_VER < 20
bool apply_sparse_flushes = false;
@@ -4229,6 +4222,7 @@ cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
dst_flags |= dep_info->pMemoryBarriers[i].dstAccessMask;
src_stages |= dep_info->pMemoryBarriers[i].srcStageMask;
dst_stages |= dep_info->pMemoryBarriers[i].dstStageMask;
/* Shader writes to buffers that could then be written by a transfer
* command (including queries).
@@ -4263,6 +4257,7 @@ cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
dst_flags |= buf_barrier->dstAccessMask;
src_stages |= buf_barrier->srcStageMask;
dst_stages |= buf_barrier->dstStageMask;
/* Shader writes to buffers that could then be written by a transfer
* command (including queries).
@@ -4295,6 +4290,7 @@ cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
dst_flags |= img_barrier->dstAccessMask;
src_stages |= img_barrier->srcStageMask;
dst_stages |= img_barrier->dstStageMask;
ANV_FROM_HANDLE(anv_image, image, img_barrier->image);
const VkImageSubresourceRange *range = &img_barrier->subresourceRange;
@@ -4495,7 +4491,40 @@ cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
if (dst_flags & VK_ACCESS_INDIRECT_COMMAND_READ_BIT)
genX(cmd_buffer_flush_generated_draws)(cmd_buffer);
anv_add_pending_pipe_bits(cmd_buffer, bits, reason);
*out_src_stages = src_stages;
*out_dst_stages = dst_stages;
*out_bits = bits;
}
static void
cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
uint32_t n_dep_infos,
const VkDependencyInfo *dep_infos,
const char *reason)
{
switch (cmd_buffer->batch.engine_class) {
case INTEL_ENGINE_CLASS_VIDEO:
cmd_buffer_barrier_video(cmd_buffer, n_dep_infos, dep_infos);
break;
case INTEL_ENGINE_CLASS_COPY:
cmd_buffer_barrier_blitter(cmd_buffer, n_dep_infos, dep_infos);
break;
case INTEL_ENGINE_CLASS_RENDER:
case INTEL_ENGINE_CLASS_COMPUTE: {
VkPipelineStageFlags2 src_stages, dst_stages;
enum anv_pipe_bits bits;
cmd_buffer_accumulate_barrier_bits(cmd_buffer, n_dep_infos, dep_infos,
&src_stages, &dst_stages, &bits);
anv_add_pending_pipe_bits(cmd_buffer, bits, reason);
break;
}
default:
unreachable("Invalid engine class");
}
}
void genX(CmdPipelineBarrier2)(
@@ -5960,7 +5989,9 @@ void genX(CmdSetEvent2)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_event, event, _event);
if (anv_cmd_buffer_is_video_queue(cmd_buffer)) {
switch (cmd_buffer->batch.engine_class) {
case INTEL_ENGINE_CLASS_VIDEO:
case INTEL_ENGINE_CLASS_COPY:
anv_batch_emit(&cmd_buffer->batch, GENX(MI_FLUSH_DW), flush) {
flush.PostSyncOperation = WriteImmediateData;
flush.Address = anv_state_pool_state_address(
@@ -5968,33 +5999,40 @@ void genX(CmdSetEvent2)(
event->state);
flush.ImmediateData = VK_EVENT_SET;
}
return;
break;
case INTEL_ENGINE_CLASS_RENDER:
case INTEL_ENGINE_CLASS_COMPUTE: {
VkPipelineStageFlags2 src_stages = 0;
for (uint32_t i = 0; i < pDependencyInfo->memoryBarrierCount; i++)
src_stages |= pDependencyInfo->pMemoryBarriers[i].srcStageMask;
for (uint32_t i = 0; i < pDependencyInfo->bufferMemoryBarrierCount; i++)
src_stages |= pDependencyInfo->pBufferMemoryBarriers[i].srcStageMask;
for (uint32_t i = 0; i < pDependencyInfo->imageMemoryBarrierCount; i++)
src_stages |= pDependencyInfo->pImageMemoryBarriers[i].srcStageMask;
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
enum anv_pipe_bits pc_bits = 0;
if (src_stages & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
pc_bits |= ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
pc_bits |= ANV_PIPE_CS_STALL_BIT;
}
genx_batch_emit_pipe_control_write
(&cmd_buffer->batch, cmd_buffer->device->info,
cmd_buffer->state.current_pipeline, WriteImmediateData,
anv_state_pool_state_address(&cmd_buffer->device->dynamic_state_pool,
event->state),
VK_EVENT_SET, pc_bits);
break;
}
VkPipelineStageFlags2 src_stages = 0;
for (uint32_t i = 0; i < pDependencyInfo->memoryBarrierCount; i++)
src_stages |= pDependencyInfo->pMemoryBarriers[i].srcStageMask;
for (uint32_t i = 0; i < pDependencyInfo->bufferMemoryBarrierCount; i++)
src_stages |= pDependencyInfo->pBufferMemoryBarriers[i].srcStageMask;
for (uint32_t i = 0; i < pDependencyInfo->imageMemoryBarrierCount; i++)
src_stages |= pDependencyInfo->pImageMemoryBarriers[i].srcStageMask;
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
enum anv_pipe_bits pc_bits = 0;
if (src_stages & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
pc_bits |= ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
pc_bits |= ANV_PIPE_CS_STALL_BIT;
}
genx_batch_emit_pipe_control_write
(&cmd_buffer->batch, cmd_buffer->device->info,
cmd_buffer->state.current_pipeline, WriteImmediateData,
anv_state_pool_state_address(&cmd_buffer->device->dynamic_state_pool,
event->state),
VK_EVENT_SET, pc_bits);
default:
unreachable("Invalid engine class");
}
}
void genX(CmdResetEvent2)(
@@ -6005,7 +6043,9 @@ void genX(CmdResetEvent2)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_event, event, _event);
if (anv_cmd_buffer_is_video_queue(cmd_buffer)) {
switch (cmd_buffer->batch.engine_class) {
case INTEL_ENGINE_CLASS_VIDEO:
case INTEL_ENGINE_CLASS_COPY:
anv_batch_emit(&cmd_buffer->batch, GENX(MI_FLUSH_DW), flush) {
flush.PostSyncOperation = WriteImmediateData;
flush.Address = anv_state_pool_state_address(
@@ -6013,25 +6053,32 @@ void genX(CmdResetEvent2)(
event->state);
flush.ImmediateData = VK_EVENT_RESET;
}
return;
break;
case INTEL_ENGINE_CLASS_RENDER:
case INTEL_ENGINE_CLASS_COMPUTE: {
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
enum anv_pipe_bits pc_bits = 0;
if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
pc_bits |= ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
pc_bits |= ANV_PIPE_CS_STALL_BIT;
}
genx_batch_emit_pipe_control_write
(&cmd_buffer->batch, cmd_buffer->device->info,
cmd_buffer->state.current_pipeline, WriteImmediateData,
anv_state_pool_state_address(&cmd_buffer->device->dynamic_state_pool,
event->state),
VK_EVENT_RESET,
pc_bits);
break;
}
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
enum anv_pipe_bits pc_bits = 0;
if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
pc_bits |= ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
pc_bits |= ANV_PIPE_CS_STALL_BIT;
}
genx_batch_emit_pipe_control_write
(&cmd_buffer->batch, cmd_buffer->device->info,
cmd_buffer->state.current_pipeline, WriteImmediateData,
anv_state_pool_state_address(&cmd_buffer->device->dynamic_state_pool,
event->state),
VK_EVENT_RESET,
pc_bits);
default:
unreachable("Invalid engine class");
}
}
void genX(CmdWaitEvents2)(