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tu: Rename PrimID-related registers

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It turns out that the hardware automatically selects whether PrimID
passthrough needs to happen based on whether GS is enabled, which means
that it's safe to always set these registers based whether PrimID is
read by the FS and the hardware will ignore them when GS is enabled. Use
the real names for these registers to make it less confusing when we
start to do that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
This commit is contained in:
Connor Abbott
2023-05-09 19:37:21 +02:00
committed by Marge Bot
parent 979cf7bac0
commit b312155cc5
8 changed files with 26 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/freedreno/.gitlab-ci/reference/crash.log
+2 -2
View File
@@ -6233,7 +6233,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
ffffffff PC_RESTART_INDEX: 4294967295
0000001f PC_MODE_CNTL: 0x1f
00000001 PC_POWER_CNTL: 0x1
00000000 PC_PRIMID_PASSTHRU: FALSE
00000000 PC_PS_CNTL: { 0 }
00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
00000001 PC_GS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
@@ -6461,7 +6461,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
ffffffff PC_RESTART_INDEX: 4294967295
0000001f PC_MODE_CNTL: 0x1f
00000001 PC_POWER_CNTL: 0x1
00000000 PC_PRIMID_PASSTHRU: FALSE
00000000 PC_PS_CNTL: { 0 }
00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
00000001 PC_GS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
src/freedreno/.gitlab-ci/reference/crash_prefetch.log
+6 -6
View File
@@ -2869,7 +2869,7 @@ got cmdszdw=83
!+ 00ff0004 VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
!+ ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
+ 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
+ 00000000 PC_PRIMID_PASSTHRU: FALSE
+ 00000000 PC_PS_CNTL: { 0 }
+ 00000000 PC_RASTER_CNTL: { STREAM = 0 }
!+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
+ 00000000 PC_PRIMITIVE_CNTL_0: { 0 }
@@ -3583,7 +3583,7 @@ got cmdszdw=83
+ 00ff0004 VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
+ ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
+ 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
+ 00000000 PC_PRIMID_PASSTHRU: FALSE
+ 00000000 PC_PS_CNTL: { 0 }
+ 00000000 PC_RASTER_CNTL: { STREAM = 0 }
+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
+ 00000000 PC_PRIMITIVE_CNTL_0: { 0 }
@@ -4308,7 +4308,7 @@ got cmdszdw=83
+ 00ff0004 VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
+ ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
+ 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
+ 00000000 PC_PRIMID_PASSTHRU: FALSE
+ 00000000 PC_PS_CNTL: { 0 }
+ 00000000 PC_RASTER_CNTL: { STREAM = 0 }
+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
+ 00000000 PC_PRIMITIVE_CNTL_0: { 0 }
@@ -4958,7 +4958,7 @@ ESTIMATED CRASH LOCATION!
+ 00ff0004 VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
+ ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
+ 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
+ 00000000 PC_PRIMID_PASSTHRU: FALSE
+ 00000000 PC_PS_CNTL: { 0 }
+ 00000000 PC_RASTER_CNTL: { STREAM = 0 }
+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
+ 00000000 PC_PRIMITIVE_CNTL_0: { 0 }
@@ -18061,7 +18061,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
ffffffff PC_RESTART_INDEX: 4294967295
0000001f PC_MODE_CNTL: 0x1f
00000001 PC_POWER_CNTL: 0x1
00000000 PC_PRIMID_PASSTHRU: FALSE
00000000 PC_PS_CNTL: { 0 }
00000000 PC_PRIMITIVE_CNTL_0: { 0 }
00000004 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 4 | CLIP_MASK = 0 }
00000001 PC_GS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
@@ -18289,7 +18289,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
ffffffff PC_RESTART_INDEX: 4294967295
0000001f PC_MODE_CNTL: 0x1f
00000001 PC_POWER_CNTL: 0x1
00000000 PC_PRIMID_PASSTHRU: FALSE
00000000 PC_PS_CNTL: { 0 }
00000000 PC_PRIMITIVE_CNTL_0: { 0 }
00000004 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 4 | CLIP_MASK = 0 }
00000001 PC_GS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+3 -3
View File
@@ -944,8 +944,8 @@ cmdstream[0]: 265 dwords
write GRAS_VS_LAYER_CNTL (809b)
GRAS_VS_LAYER_CNTL: { 0 }
00000000010542e4: 0000: 48809b01 00000000
write PC_PRIMID_PASSTHRU (9806)
PC_PRIMID_PASSTHRU: FALSE
write PC_PS_CNTL (9806)
PC_PS_CNTL: { 0 }
00000000010542ec: 0000: 40980601 00000000
write VPC_CNTL_0 (9304)
VPC_CNTL_0: { NUMNONPOSVAR = 4 | PRIMIDLOC = 255 | VARYING | VIEWIDLOC = 255 }
@@ -1393,7 +1393,7 @@ cmdstream[0]: 265 dwords
!+ ff01ff04 VPC_CNTL_0: { NUMNONPOSVAR = 4 | PRIMIDLOC = 255 | VARYING | VIEWIDLOC = 255 }
+ 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
!+ ffffffff PC_RESTART_INDEX: 4294967295
+ 00000000 PC_PRIMID_PASSTHRU: FALSE
+ 00000000 PC_PS_CNTL: { 0 }
!+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
+ 00000000 PC_PRIMITIVE_CNTL_0: { 0 }
!+ 00000008 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 8 | CLIP_MASK = 0 }
src/freedreno/.gitlab-ci/reference/fd-clouds.log
+3 -3
View File
@@ -122,8 +122,8 @@ cmdstream[0]: 1023 dwords
write VPC_SO_DISABLE (9306)
VPC_SO_DISABLE: { DISABLE }
0000000001d91134: 0000: 48930601 00000001
write PC_PRIMID_PASSTHRU (9806)
PC_PRIMID_PASSTHRU: FALSE
write PC_PS_CNTL (9806)
PC_PS_CNTL: { 0 }
0000000001d9113c: 0000: 40980601 00000000
write 0x9990 (9990)
0x9990: 00000000
@@ -1029,7 +1029,7 @@ cmdstream[0]: 1023 dwords
!+ ffffffff PC_RESTART_INDEX: 4294967295
!+ 0000001f PC_MODE_CNTL: 0x1f
!+ 00000001 PC_POWER_CNTL: 0x1
+ 00000000 PC_PRIMID_PASSTHRU: FALSE
+ 00000000 PC_PS_CNTL: { 0 }
+ 00000000 PC_RASTER_CNTL: { STREAM = 0 }
!+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
+ 00000000 0x9990: 00000000
src/freedreno/.gitlab-ci/reference/prefetch-test.log
+3 -3
View File
@@ -3137,7 +3137,7 @@ got cmdszdw=438
!+ ff01ff02 VPC_CNTL_0: { NUMNONPOSVAR = 2 | PRIMIDLOC = 255 | VARYING | VIEWIDLOC = 255 }
!+ 00000000 VPC_SO_DISABLE: { 0 }
!+ ffffffff PC_RESTART_INDEX: 4294967295
+ 00000000 PC_PRIMID_PASSTHRU: FALSE
+ 00000000 PC_PS_CNTL: { 0 }
!+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
!+ 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
!+ 00000006 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 6 | CLIP_MASK = 0 }
@@ -152040,7 +152040,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
ffffffff PC_RESTART_INDEX: 4294967295
0000001f PC_MODE_CNTL: 0x1f
00000000 PC_POWER_CNTL: 0
00000000 PC_PRIMID_PASSTHRU: FALSE
00000000 PC_PS_CNTL: { 0 }
00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
00000006 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 6 | CLIP_MASK = 0 }
00000001 PC_GS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
@@ -152268,7 +152268,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
ffffffff PC_RESTART_INDEX: 4294967295
0000001f PC_MODE_CNTL: 0x1f
00000000 PC_POWER_CNTL: 0
00000000 PC_PRIMID_PASSTHRU: FALSE
00000000 PC_PS_CNTL: { 0 }
00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST }
00000006 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 6 | CLIP_MASK = 0 }
00000001 PC_GS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 }
src/freedreno/registers/adreno/a6xx.xml
+5 -6
View File
@@ -2940,8 +2940,9 @@ to upconvert to 32b float internally?
<reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
<!-- probably a mirror of VFD_CONTROL_6 -->
<reg32 offset="0x9806" name="PC_PRIMID_PASSTHRU" pos="0" type="boolean" usage="rp_blit"/>
<reg32 offset="0x9806" name="PC_PS_CNTL" usage="rp_blit">
<bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/>
</reg32>
<!-- New in a6xx gen3+ -->
<reg32 offset="0x9808" name="PC_SO_STREAM_CNTL" usage="rp_blit">
@@ -3122,11 +3123,9 @@ to upconvert to 32b float internally?
</reg32>
<reg32 offset="0xa006" name="VFD_CONTROL_6" usage="rp_blit">
<!--
True if gl_PrimitiveID is read via the FS and there is
no matching write from the GS, and therefore it needs to
be passed through via fixed-function logic.
True if gl_PrimitiveID is read via the FS
-->
<bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
<bitfield name="PRIMID4PSEN" pos="0" type="boolean"/>
</reg32>
<reg32 offset="0xa007" name="VFD_MODE_CNTL" usage="cmd">
src/freedreno/vulkan/tu_pipeline.cc
+2 -2
View File
@@ -896,7 +896,7 @@ tu6_emit_vs_system_values(struct tu_cs *cs,
tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
0xfc00); /* VFD_CONTROL_5 */
tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID4PSEN)); /* VFD_CONTROL_6 */
}
static void
@@ -1437,7 +1437,7 @@ tu6_emit_vpc(struct tu_cs *cs,
tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER) |
CONDREG(view_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW));
tu_cs_emit_regs(cs, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
tu_cs_emit_regs(cs, A6XX_PC_PS_CNTL(.primitiveiden = primid_passthru));
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
+2 -2
View File
@@ -1141,7 +1141,7 @@ setup_stateobj(struct fd_screen *screen, struct fd_ringbuffer *ring,
if (fs->instrlen)
fd6_emit_shader(ctx, ring, fs);
OUT_REG(ring, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
OUT_REG(ring, A6XX_PC_PS_CNTL(.primitiveiden = primid_passthru));
uint32_t non_sysval_input_count = 0;
for (uint32_t i = 0; i < vs->inputs_count; i++)
@@ -1176,7 +1176,7 @@ setup_stateobj(struct fd_screen *screen, struct fd_ringbuffer *ring,
OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
0xfc00); /* VFD_CONTROL_5 */
OUT_RING(ring, COND(primid_passthru,
A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
A6XX_VFD_CONTROL_6_PRIMID4PSEN)); /* VFD_CONTROL_6 */
if (!binning_pass)
fd6_emit_immediates(ctx->screen, fs, ring);