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etnaviv: rs: unconditionally flush color and depth cache before using RS

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When the RS uses the pixel pipes it seems to destroy/invalidate any
content sitting in the color and depth caches from a previous draw.
Always flush the color and depth cache before using the RS to make
sure that any cache content written by the PE is properly flushed
to memory.

Fixes spec@!opengl 1.0@gl-1.0-drawpixels-depth-test and probably a
few others that are suffering from corruption of PE writes.

CC: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23530>
This commit is contained in:
Lucas Stach
2023-06-08 22:03:41 +02:00
committed by Marge Bot
parent cfc1be9590
commit b1cd5780d6
1 changed files with 6 additions and 15 deletions
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21
src/gallium/drivers/etnaviv/etnaviv_rs.c
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@@ -731,21 +731,12 @@ etna_try_rs_blit(struct pipe_context *pctx,
width & (w_align - 1) || height & (h_align - 1))
goto manual;
/* Always flush color and depth cache together before resolving. This works
* around artifacts that appear in some cases when scanning out a texture
* directly after it has been rendered to, such as rendering an animated web
* page in a QtWebEngine based WebView on GC2000. The artifacts look like
* the texture sampler samples zeroes instead of texture data in a small,
* irregular triangle in the lower right of each browser tile quad. Other
* attempts to avoid these artifacts, including a pipeline stall before the
* color flush or a TS cache flush afterwards, or flushing multiple times,
* with stalls before and after each flush, have shown no effect. */
if (src->base.bind & PIPE_BIND_RENDER_TARGET ||
src->base.bind & PIPE_BIND_DEPTH_STENCIL) {
etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
}
/* Always flush color and depth cache together before resolving. This makes
* sure that all previous cache content written by the PE is flushed out
* before RS uses the pixel pipes, which invalidates those caches. */
etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
/* Set up color TS to source surface before blit, if needed */
bool source_ts_valid = false;