intel/blorp: Conditionally clear full surface depth and stencil
We should set "Full Surface Depth and Stencil Clear" field of WM_HZ_OP 3DSTATE packet, only when application requires the entire depth surface to be cleared. Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6549>
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@@ -846,6 +846,29 @@ blorp_can_hiz_clear_depth(const struct gen_device_info *devinfo,
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return isl_aux_usage_has_hiz(aux_usage);
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}
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static bool
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blorp_can_clear_full_surface(const struct blorp_surf *depth,
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const struct blorp_surf *stencil,
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uint32_t level,
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uint32_t x0, uint32_t y0,
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uint32_t x1, uint32_t y1,
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bool clear_depth,
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bool clear_stencil)
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{
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uint32_t width = 0, height = 0;
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if (clear_stencil) {
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width = minify(stencil->surf->logical_level0_px.width, level);
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height = minify(stencil->surf->logical_level0_px.height, level);
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}
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if (clear_depth && !(width || height)) {
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width = minify(depth->surf->logical_level0_px.width, level);
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height = minify(depth->surf->logical_level0_px.height, level);
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}
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return x0 == 0 && y0 == 0 && width == x1 && height == y1;
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}
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void
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blorp_hiz_clear_depth_stencil(struct blorp_batch *batch,
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const struct blorp_surf *depth,
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@@ -864,6 +887,14 @@ blorp_hiz_clear_depth_stencil(struct blorp_batch *batch,
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assert(ISL_DEV_GEN(batch->blorp->isl_dev) >= 8);
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params.hiz_op = ISL_AUX_OP_FAST_CLEAR;
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/* From BSpec: 3DSTATE_WM_HZ_OP_BODY >> Full Surface Depth and Stencil Clear
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*
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* "Software must set this only when the APP requires the entire Depth
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* surface to be cleared."
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*/
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params.full_surface_hiz_op =
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blorp_can_clear_full_surface(depth, stencil, level, x0, y0, x1, y1,
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clear_depth, clear_stencil);
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params.num_layers = 1;
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params.x0 = x0;
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