AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

nir: add shader_info::tess::tcs_cross_invocation_outputs_written

Browse Source 
for AMD

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34863>
This commit is contained in:
Marek Olšák
2025-04-19 01:23:57 -04:00
committed by Marge Bot
parent f45356f4ac
commit afd8fefb79
2 changed files with 16 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/compiler/nir/nir_gather_info.c
+9
View File
@@ -181,6 +181,9 @@ set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
shader->info.outputs_written |= bitfield;
if (indirect)
shader->info.outputs_accessed_indirectly |= bitfield;
if (cross_invocation && shader->info.stage == MESA_SHADER_TESS_CTRL)
shader->info.tess.tcs_cross_invocation_outputs_written |= bitfield;
}
}
@@ -630,6 +633,11 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
}
}
if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
instr->intrinsic == nir_intrinsic_store_per_vertex_output &&
!src_is_invocation_id(nir_get_io_arrayed_index_src(instr)))
shader->info.tess.tcs_cross_invocation_outputs_written |= slot_mask;
if (shader->info.stage == MESA_SHADER_MESH &&
(instr->intrinsic == nir_intrinsic_store_per_vertex_output ||
instr->intrinsic == nir_intrinsic_store_per_primitive_output) &&
@@ -1020,6 +1028,7 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
shader->info.tess.tcs_same_invocation_inputs_read = 0;
shader->info.tess.tcs_cross_invocation_inputs_read = 0;
shader->info.tess.tcs_cross_invocation_outputs_read = 0;
shader->info.tess.tcs_cross_invocation_outputs_written = 0;
}
if (shader->info.stage == MESA_SHADER_MESH) {
shader->info.mesh.ms_cross_invocation_output_access = 0;
src/compiler/shader_info.h
+7 -2
View File
@@ -519,15 +519,20 @@ typedef struct shader_info {
*/
uint64_t tcs_same_invocation_inputs_read;
/* Bit mask of TCS per-vertex inputs (VS outputs) that are used
/* Bit mask of TCS per-vertex inputs (VS outputs) that are read
* with a vertex index that is NOT the invocation id
*/
uint64_t tcs_cross_invocation_inputs_read;
/* Bit mask of TCS per-vertex outputs that are used
/* Bit mask of TCS per-vertex outputs that are read
* with a vertex index that is NOT the invocation id
*/
uint64_t tcs_cross_invocation_outputs_read;
/* Bit mask of TCS per-vertex outputs that are written
* with a vertex index that is NOT the invocation id
*/
uint64_t tcs_cross_invocation_outputs_written;
} tess;
/* Applies to MESH and TASK. */