iris: Optimize genX(emit_depth_state_workarounds)
Only emit the workaround as needed. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
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@@ -1143,6 +1143,14 @@ struct iris_depth_buffer_state {
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GENX(3DSTATE_CLEAR_PARAMS_length)];
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};
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#if GFX_VERx10 == 120
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enum iris_depth_reg_mode {
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IRIS_DEPTH_REG_MODE_HW_DEFAULT = 0,
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IRIS_DEPTH_REG_MODE_D16,
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IRIS_DEPTH_REG_MODE_UNKNOWN,
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};
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#endif
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/**
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* Generation-specific context state (ice->state.genx->...).
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*
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@@ -1166,6 +1174,10 @@ struct iris_genx_state {
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bool object_preemption;
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#endif
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#if GFX_VERx10 == 120
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enum iris_depth_reg_mode depth_reg_mode;
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#endif
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struct {
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#if GFX_VER == 8
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struct brw_image_param image_param[PIPE_MAX_SHADER_IMAGES];
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@@ -5537,6 +5549,19 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice,
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#if GFX_VERx10 == 120
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const bool fmt_is_d16 = surf->format == ISL_FORMAT_R16_UNORM;
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switch (ice->state.genx->depth_reg_mode) {
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case IRIS_DEPTH_REG_MODE_HW_DEFAULT:
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if (!fmt_is_d16)
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return;
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break;
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case IRIS_DEPTH_REG_MODE_D16:
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if (fmt_is_d16)
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return;
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break;
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case IRIS_DEPTH_REG_MODE_UNKNOWN:
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break;
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}
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/* We'll change some CHICKEN registers depending on the depth surface
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* format. Do a depth flush and stall so the pipeline is not using these
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* settings while we change the registers.
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@@ -5564,6 +5589,9 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice,
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reg.HZDepthTestLEGEOptimizationDisable = fmt_is_d16;
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reg.HZDepthTestLEGEOptimizationDisableMask = true;
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}
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ice->state.genx->depth_reg_mode =
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fmt_is_d16 ? IRIS_DEPTH_REG_MODE_D16 : IRIS_DEPTH_REG_MODE_HW_DEFAULT;
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#endif
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}
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@@ -7872,6 +7900,10 @@ iris_lost_genx_state(struct iris_context *ice, struct iris_batch *batch)
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{
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struct iris_genx_state *genx = ice->state.genx;
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#if GFX_VERx10 == 120
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genx->depth_reg_mode = IRIS_DEPTH_REG_MODE_UNKNOWN;
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#endif
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memset(genx->last_index_buffer, 0, sizeof(genx->last_index_buffer));
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}
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