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radv: simplify emitting SQTT shaders relocation for GFX6-GFX11.5

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36188>
This commit is contained in:
Samuel Pitoiset
2025-07-21 14:07:08 +02:00
committed by Marge Bot
parent 9965a344ae
commit aa80a08598
1 changed files with 13 additions and 126 deletions
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139
src/amd/vulkan/layers/radv_sqtt_layer.c
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@@ -17,127 +17,6 @@
#include "ac_rgp.h"
#include "ac_sqtt.h"
static void
radv_gfx12_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv_graphics_pipeline *pipeline)
{
struct radv_sqtt_shaders_reloc *reloc = pipeline->sqtt_shaders_reloc;
radv_foreach_stage (s, RADV_GRAPHICS_STAGE_BITS & ~VK_SHADER_STAGE_TASK_BIT_EXT) {
const struct radv_shader *shader = pipeline->base.shaders[s];
if (!shader)
continue;
/* Shaders are allocated in the 32-bit addr space and high bits are already configured. */
gfx12_push_sh_reg(cmd_buffer, shader->info.regs.pgm_lo, reloc->va[s] >> 8);
}
}
static void
radv_gfx6_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv_graphics_pipeline *pipeline)
{
const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
struct radv_sqtt_shaders_reloc *reloc = pipeline->sqtt_shaders_reloc;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va;
radeon_begin(cs);
/* VS */
if (pipeline->base.shaders[MESA_SHADER_VERTEX]) {
const struct radv_shader *vs = pipeline->base.shaders[MESA_SHADER_VERTEX];
va = reloc->va[MESA_SHADER_VERTEX];
if (vs->info.vs.as_ls) {
radeon_set_sh_reg(vs->info.regs.pgm_lo, va >> 8);
} else if (vs->info.vs.as_es) {
radeon_set_sh_reg_seq(vs->info.regs.pgm_lo, 2);
radeon_emit(va >> 8);
radeon_emit(S_00B324_MEM_BASE(va >> 40));
} else if (vs->info.is_ngg) {
radeon_set_sh_reg(vs->info.regs.pgm_lo, va >> 8);
} else {
radeon_set_sh_reg_seq(vs->info.regs.pgm_lo, 2);
radeon_emit(va >> 8);
radeon_emit(S_00B124_MEM_BASE(va >> 40));
}
}
/* TCS */
if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]) {
const struct radv_shader *tcs = pipeline->base.shaders[MESA_SHADER_TESS_CTRL];
va = reloc->va[MESA_SHADER_TESS_CTRL];
if (pdev->info.gfx_level >= GFX9) {
radeon_set_sh_reg(tcs->info.regs.pgm_lo, va >> 8);
} else {
radeon_set_sh_reg_seq(tcs->info.regs.pgm_lo, 2);
radeon_emit(va >> 8);
radeon_emit(S_00B424_MEM_BASE(va >> 40));
}
}
/* TES */
if (pipeline->base.shaders[MESA_SHADER_TESS_EVAL]) {
const struct radv_shader *tes = pipeline->base.shaders[MESA_SHADER_TESS_EVAL];
va = reloc->va[MESA_SHADER_TESS_EVAL];
if (tes->info.is_ngg) {
radeon_set_sh_reg(tes->info.regs.pgm_lo, va >> 8);
} else if (tes->info.tes.as_es) {
radeon_set_sh_reg_seq(tes->info.regs.pgm_lo, 2);
radeon_emit(va >> 8);
radeon_emit(S_00B324_MEM_BASE(va >> 40));
} else {
radeon_set_sh_reg_seq(tes->info.regs.pgm_lo, 2);
radeon_emit(va >> 8);
radeon_emit(S_00B124_MEM_BASE(va >> 40));
}
}
/* GS */
if (pipeline->base.shaders[MESA_SHADER_GEOMETRY]) {
const struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
va = reloc->va[MESA_SHADER_GEOMETRY];
if (gs->info.is_ngg) {
radeon_set_sh_reg(gs->info.regs.pgm_lo, va >> 8);
} else {
if (pdev->info.gfx_level >= GFX9) {
radeon_set_sh_reg(gs->info.regs.pgm_lo, va >> 8);
} else {
radeon_set_sh_reg_seq(gs->info.regs.pgm_lo, 2);
radeon_emit(va >> 8);
radeon_emit(S_00B224_MEM_BASE(va >> 40));
}
}
}
/* FS */
if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]) {
const struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
va = reloc->va[MESA_SHADER_FRAGMENT];
radeon_set_sh_reg_seq(ps->info.regs.pgm_lo, 2);
radeon_emit(va >> 8);
radeon_emit(S_00B024_MEM_BASE(va >> 40));
}
/* MS */
if (pipeline->base.shaders[MESA_SHADER_MESH]) {
const struct radv_shader *ms = pipeline->base.shaders[MESA_SHADER_MESH];
va = reloc->va[MESA_SHADER_MESH];
radeon_set_sh_reg(ms->info.regs.pgm_lo, va >> 8);
}
radeon_end();
}
void
radv_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv_graphics_pipeline *pipeline)
{
@@ -146,12 +25,20 @@ radv_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv
struct radv_sqtt_shaders_reloc *reloc = pipeline->sqtt_shaders_reloc;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
radv_cs_add_buffer(device->ws, cs, reloc->bo);
radv_foreach_stage (s, RADV_GRAPHICS_STAGE_BITS & ~VK_SHADER_STAGE_TASK_BIT_EXT) {
const struct radv_shader *shader = pipeline->base.shaders[s];
if (pdev->info.gfx_level >= GFX12) {
radv_gfx12_sqtt_emit_relocated_shaders(cmd_buffer, pipeline);
} else {
radv_gfx6_sqtt_emit_relocated_shaders(cmd_buffer, pipeline);
if (!shader)
continue;
/* Shaders are allocated in the 32-bit addr space and high bits are already configured. */
if (pdev->info.gfx_level >= GFX12) {
gfx12_push_sh_reg(cmd_buffer, shader->info.regs.pgm_lo, reloc->va[s] >> 8);
} else {
radeon_begin(cs);
radeon_set_sh_reg(shader->info.regs.pgm_lo, reloc->va[s] >> 8);
radeon_end();
}
}
}