agx: Inline 16-bit load/store offsets

Most integer immediates are only 8-bit, but load/store instructions allow their
immediate offsets to be 16-bit instead. Take advantage of this in the optimizer.
This eliminates 36% of the instructions in
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.36, a fitting
percentage.

Insignificant effect on dEQP-GLES31.functional.ssbo.* performance... Only a
small % of our compile-time pie is actually spent in the backend anyway (as
opposed to NIR passes or GLSL IR).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21430>

src/asahi/compiler/agx_optimizer.c

@@ -123,6 +123,8 @@ agx_optimizer_inline_imm(agx_instr **defs, agx_instr *I, unsigned srcs,
          continue;
 
       uint8_t value = def->imm;
+      uint16_t value_u16 = def->imm;
+
       bool float_src = is_float;
 
       /* cmpselsrc takes integer immediates only */
@@ -152,6 +154,8 @@ agx_optimizer_inline_imm(agx_instr **defs, agx_instr *I, unsigned srcs,
          I->src[s] = agx_immediate_f(f);
       } else if (value == def->imm) {
          I->src[s] = agx_immediate(value);
+      } else if (value_u16 == def->imm && agx_allows_16bit_immediate(I)) {
+         I->src[s] = agx_abs(agx_immediate(value_u16));
       }
    }
 }