mesa: add GLSL support for DP2, NRM3, NRM4 instructions (not actually emitted yet though)
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@@ -413,6 +413,9 @@ static slang_asm_info AsmInfo[] = {
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{ "vec4_multiply", IR_MUL, 1, 2 },
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{ "vec4_dot", IR_DOT4, 1, 2 },
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{ "vec3_dot", IR_DOT3, 1, 2 },
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{ "vec2_dot", IR_DOT2, 1, 2 },
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{ "vec3_nrm", IR_NRM3, 1, 1 },
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{ "vec4_nrm", IR_NRM4, 1, 1 },
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{ "vec3_cross", IR_CROSS, 1, 2 },
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{ "vec4_lrp", IR_LRP, 1, 3 },
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{ "vec4_min", IR_MIN, 1, 2 },
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@@ -488,6 +488,9 @@ instruction_annotation(gl_inst_opcode opcode, char *dstAnnot,
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case OPCODE_MUL:
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operator = "*";
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break;
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case OPCODE_DP2:
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operator = "DP2";
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break;
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case OPCODE_DP3:
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operator = "DP3";
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break;
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@@ -708,7 +711,7 @@ emit_compare(slang_emit_info *emitInfo, slang_ir_node *n)
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}
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else {
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assert(size == 2);
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dotOp = OPCODE_DP3;
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dotOp = OPCODE_DP3; /* XXX use OPCODE_DP2 eventually */
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swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y);
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}
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@@ -1893,12 +1896,15 @@ emit(slang_emit_info *emitInfo, slang_ir_node *n)
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case IR_NOISE2:
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case IR_NOISE3:
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case IR_NOISE4:
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case IR_NRM4:
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case IR_NRM3:
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/* binary */
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case IR_ADD:
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case IR_SUB:
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case IR_MUL:
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case IR_DOT4:
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case IR_DOT3:
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case IR_DOT2:
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case IR_CROSS:
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case IR_MIN:
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case IR_MAX:
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@@ -37,8 +37,11 @@ static const slang_ir_info IrInfo[] = {
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{ IR_SUB, "IR_SUB", OPCODE_SUB, 4, 2 },
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{ IR_MUL, "IR_MUL", OPCODE_MUL, 4, 2 },
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{ IR_DIV, "IR_DIV", OPCODE_NOP, 0, 2 }, /* XXX broke */
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{ IR_DOT4, "IR_DOT_4", OPCODE_DP4, 1, 2 },
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{ IR_DOT3, "IR_DOT_3", OPCODE_DP3, 1, 2 },
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{ IR_DOT4, "IR_DOT4", OPCODE_DP4, 1, 2 },
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{ IR_DOT3, "IR_DOT3", OPCODE_DP3, 1, 2 },
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{ IR_DOT2, "IR_DOT2", OPCODE_DP2, 1, 2 },
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{ IR_NRM4, "IR_NRM4", OPCODE_NRM4, 1, 1 },
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{ IR_NRM3, "IR_NRM3", OPCODE_NRM3, 1, 1 },
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{ IR_CROSS, "IR_CROSS", OPCODE_XPD, 3, 2 },
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{ IR_LRP, "IR_LRP", OPCODE_LRP, 4, 3 },
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{ IR_MIN, "IR_MIN", OPCODE_MIN, 4, 2 },
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@@ -83,6 +83,9 @@ typedef enum
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IR_DIV,
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IR_DOT4,
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IR_DOT3,
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IR_DOT2,
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IR_NRM4,
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IR_NRM3,
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IR_CROSS, /* vec3 cross product */
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IR_LRP,
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IR_CLAMP,
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