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radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2)

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This fixes arb_shader_image_load_store-host-mem-barrier.

v2: flush TC L2 for index buffers on <= CIK (Marek)

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle
2016-03-16 20:47:47 -05:00
parent fc94bc2986
commit a8f5d11426
1 changed files with 12 additions and 2 deletions
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src/gallium/drivers/radeonsi/si_state.c
+12 -2
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@@ -3537,18 +3537,28 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
PIPE_BARRIER_SHADER_BUFFER |
PIPE_BARRIER_TEXTURE |
PIPE_BARRIER_IMAGE)) {
PIPE_BARRIER_IMAGE |
PIPE_BARRIER_STREAMOUT_BUFFER)) {
/* As far as I can tell, L1 contents are written back to L2
* automatically at end of shader, but the contents of other
* L1 caches might still be stale. */
sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
}
if (flags & PIPE_BARRIER_INDEX_BUFFER) {
sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
/* Indices are read through TC L2 since VI. */
if (sctx->screen->b.chip_class <= CIK)
sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
}
if (flags & PIPE_BARRIER_FRAMEBUFFER)
sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
PIPE_BARRIER_FRAMEBUFFER)) {
PIPE_BARRIER_FRAMEBUFFER |
PIPE_BARRIER_INDIRECT_BUFFER)) {
/* Not sure if INV_GLOBAL_L2 is the best thing here.
*
* We need to make sure that TC L1 & L2 are written back to