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i965: Take a uint64_t immediate in emit_pipe_control_write

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It's a 64-bit value.  Splitting it up just makes the function arguments
awkward.

Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand
2017-06-13 09:56:31 -07:00
parent 86da08367b
commit a8ea68bc93
4 changed files with 14 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_context.h
+1 -1
View File
@@ -1653,7 +1653,7 @@ void brw_fini_pipe_control(struct brw_context *brw);
void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
struct brw_bo *bo, uint32_t offset,
uint32_t imm_lower, uint32_t imm_upper);
uint64_t imm);
void brw_emit_mi_flush(struct brw_context *brw);
void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
void brw_emit_depth_stall_flushes(struct brw_context *brw);
src/mesa/drivers/dri/i965/brw_pipe_control.c
+10 -12
View File
@@ -178,7 +178,7 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
void
brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
struct brw_bo *bo, uint32_t offset,
uint32_t imm_lower, uint32_t imm_upper)
uint64_t imm)
{
if (brw->gen >= 8) {
if (brw->gen == 8)
@@ -189,8 +189,8 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
OUT_BATCH(flags);
OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
offset);
OUT_BATCH(imm_lower);
OUT_BATCH(imm_upper);
OUT_BATCH(imm);
OUT_BATCH(imm >> 32);
ADVANCE_BATCH();
} else if (brw->gen >= 6) {
flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
@@ -205,16 +205,16 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
OUT_BATCH(flags);
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
gen6_gtt | offset);
OUT_BATCH(imm_lower);
OUT_BATCH(imm_upper);
OUT_BATCH(imm);
OUT_BATCH(imm >> 32);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
OUT_BATCH(imm_lower);
OUT_BATCH(imm_upper);
OUT_BATCH(imm);
OUT_BATCH(imm >> 32);
ADVANCE_BATCH();
}
}
@@ -264,8 +264,7 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_IMMEDIATE
| PIPE_CONTROL_DEPTH_STALL,
brw->workaround_bo, 0,
0, 0);
brw->workaround_bo, 0, 0);
}
@@ -278,8 +277,7 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_CS_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE,
brw->workaround_bo, 0,
0, 0);
brw->workaround_bo, 0, 0);
}
@@ -328,7 +326,7 @@ brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
PIPE_CONTROL_STALL_AT_SCOREBOARD);
brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
brw->workaround_bo, 0, 0, 0);
brw->workaround_bo, 0, 0);
}
/* Emit a pipelined flush to either flush render and texture cache for
src/mesa/drivers/dri/i965/brw_queryobj.c
+2 -3
View File
@@ -97,7 +97,7 @@ brw_write_timestamp(struct brw_context *brw, struct brw_bo *query_bo, int idx)
flags |= PIPE_CONTROL_CS_STALL;
brw_emit_pipe_control_write(brw, flags,
query_bo, idx * sizeof(uint64_t), 0, 0);
query_bo, idx * sizeof(uint64_t), 0);
}
/**
@@ -120,8 +120,7 @@ brw_write_depth_count(struct brw_context *brw, struct brw_bo *query_bo, int idx)
}
brw_emit_pipe_control_write(brw, flags,
query_bo, idx * sizeof(uint64_t),
0, 0);
query_bo, idx * sizeof(uint64_t), 0);
}
/**
src/mesa/drivers/dri/i965/gen6_queryobj.c
+1 -1
View File
@@ -72,7 +72,7 @@ set_query_availability(struct brw_context *brw, struct brw_query_object *query,
brw_emit_pipe_control_write(brw, flags,
query->bo, 2 * sizeof(uint64_t),
available, 0);
available);
}
}