AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radv: Add gs/hs_inputs_read field for linked LS and ES.

Browse Source 
This will be used in the following commits to determine the
memory locations for LS/HS and ES/GS linking.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29812>
This commit is contained in:
Timur Kristóf
2024-06-20 17:03:34 +02:00
committed by Marge Bot
parent 5daf06e829
commit a8d78f889e
2 changed files with 12 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_shader_info.c
+10
View File
@@ -493,6 +493,9 @@ gather_shader_info_vs(struct radv_device *device, const nir_shader *nir,
info->vs.dynamic_inputs = true;
}
info->gs_inputs_read = ~0ULL;
info->vs.hs_inputs_read = ~0ULL;
/* Use per-attribute vertex descriptors to prevent faults and for correct bounds checking. */
info->vs.use_per_attribute_vb_descs = radv_use_per_attribute_vb_descs(nir, gfx_state, stage_key);
@@ -574,6 +577,7 @@ gather_shader_info_tcs(struct radv_device *device, const nir_shader *nir,
static void
gather_shader_info_tes(struct radv_device *device, const nir_shader *nir, struct radv_shader_info *info)
{
info->gs_inputs_read = ~0ULL;
info->tes._primitive_mode = nir->info.tess._primitive_mode;
info->tes.spacing = nir->info.tess.spacing;
info->tes.ccw = nir->info.tess.ccw;
@@ -1726,12 +1730,18 @@ radv_link_shaders_info(struct radv_device *device, struct radv_shader_stage *pro
es_info->workgroup_size = gs_info->workgroup_size;
}
if (consumer && consumer->stage == MESA_SHADER_GEOMETRY) {
producer->info.gs_inputs_read = consumer->nir->info.inputs_read;
}
}
if (producer->stage == MESA_SHADER_VERTEX && consumer && consumer->stage == MESA_SHADER_TESS_CTRL) {
struct radv_shader_stage *vs_stage = producer;
struct radv_shader_stage *tcs_stage = consumer;
vs_stage->info.vs.hs_inputs_read = tcs_stage->nir->info.inputs_read;
if (gfx_state->ts.patch_control_points) {
vs_stage->info.workgroup_size =
ac_compute_lshs_workgroup_size(pdev->info.gfx_level, MESA_SHADER_VERTEX, tcs_stage->info.num_tess_patches,
src/amd/vulkan/radv_shader_info.h
+2
View File
@@ -109,6 +109,7 @@ struct radv_shader_info {
bool has_epilog; /* Only for TCS or PS */
bool merged_shader_compiled_separately; /* GFX9+ */
bool force_indirect_desc_sets;
uint64_t gs_inputs_read; /* Mask of GS inputs read (only used by linked ES) */
struct {
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
@@ -127,6 +128,7 @@ struct radv_shader_info {
bool dynamic_inputs;
bool dynamic_num_verts_per_prim;
uint32_t num_outputs; /* For NGG streamout only */
uint64_t hs_inputs_read; /* Mask of HS inputs read (only used by linked LS) */
} vs;
struct {
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];