AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radeonsi: assume LLVM 3.4.2 is always present

Browse Source 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák
2014-07-08 02:50:57 +02:00
parent 4ad682461e
commit a66d934139
6 changed files with 7 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeon/r600_pipe_common.c
-7
View File
@@ -401,12 +401,6 @@ const char *r600_get_llvm_processor_name(enum radeon_family family)
case CHIP_PITCAIRN: return "pitcairn";
case CHIP_VERDE: return "verde";
case CHIP_OLAND: return "oland";
#if HAVE_LLVM <= 0x0303
default:
fprintf(stderr, "%s: Unknown chipset = %i, defaulting to Southern Islands\n",
__func__, family);
return "SI";
#else
case CHIP_HAINAN: return "hainan";
case CHIP_BONAIRE: return "bonaire";
case CHIP_KABINI: return "kabini";
@@ -419,7 +413,6 @@ const char *r600_get_llvm_processor_name(enum radeon_family family)
return "kabini";
#endif
default: return "";
#endif
}
}
src/gallium/drivers/radeonsi/si_descriptors.c
+2 -4
View File
@@ -152,11 +152,11 @@ static void si_update_descriptors(struct si_context *sctx,
7 + /* copy */
(4 + desc->element_dw_size) * util_bitcount(desc->dirty_mask) + /* update */
4; /* pointer update */
#if LLVM_SUPPORTS_GEOM_SHADERS
if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 &&
desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0)
desc->atom.num_dw += 4; /* second pointer update */
#endif
desc->atom.dirty = true;
/* The descriptors are read with the K cache. */
sctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
@@ -177,7 +177,6 @@ static void si_emit_shader_pointer(struct si_context *sctx,
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
#if LLVM_SUPPORTS_GEOM_SHADERS
if (desc->shader_userdata_reg >= R_00B130_SPI_SHADER_USER_DATA_VS_0 &&
desc->shader_userdata_reg < R_00B230_SPI_SHADER_USER_DATA_GS_0) {
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
@@ -188,7 +187,6 @@ static void si_emit_shader_pointer(struct si_context *sctx,
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
}
#endif
}
static void si_emit_descriptors(struct si_context *sctx,
src/gallium/drivers/radeonsi/si_pipe.c
+4 -8
View File
@@ -218,8 +218,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_MULTISAMPLE:
/* 2D tiling on CIK is supported since DRM 2.35.0 */
return HAVE_LLVM >= 0x0304 && (sscreen->b.chip_class < CIK ||
sscreen->b.info.drm_minor >= 35);
return sscreen->b.chip_class < CIK ||
sscreen->b.info.drm_minor >= 35;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return R600_MAP_BUFFER_ALIGNMENT;
@@ -229,7 +229,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
return 4;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
return (LLVM_SUPPORTS_GEOM_SHADERS) ? 330 : 140;
return 330;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
@@ -317,11 +317,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
{
case PIPE_SHADER_FRAGMENT:
case PIPE_SHADER_VERTEX:
break;
case PIPE_SHADER_GEOMETRY:
#if !(LLVM_SUPPORTS_GEOM_SHADERS)
return 0;
#endif
break;
case PIPE_SHADER_COMPUTE:
switch (param) {
@@ -421,7 +417,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
}
sscreen->b.has_cp_dma = true;
sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
sscreen->b.has_streamout = true;
if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
src/gallium/drivers/radeonsi/si_pipe.h
-4
View File
@@ -39,10 +39,6 @@
#define SI_MAX_DRAW_CS_DWORDS 18
#define LLVM_SUPPORTS_GEOM_SHADERS \
((HAVE_LLVM >= 0x0305) || \
(HAVE_LLVM == 0x0304 && LLVM_VERSION_PATCH >= 1))
struct si_pipe_compute;
struct si_screen {
src/gallium/drivers/radeonsi/si_shader.c
-14
View File
@@ -69,9 +69,7 @@ struct si_shader_context
int param_instance_id;
LLVMValueRef const_md;
LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
#if HAVE_LLVM >= 0x0304
LLVMValueRef ddxy_lds;
#endif
LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
LLVMValueRef *resources;
LLVMValueRef *samplers;
@@ -2111,8 +2109,6 @@ static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
}
}
#if HAVE_LLVM >= 0x0304
static void si_llvm_emit_ddxy(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
@@ -2181,8 +2177,6 @@ static void si_llvm_emit_ddxy(
emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
}
#endif /* HAVE_LLVM >= 0x0304 */
/* Emit one vertex from the geometry shader */
static void si_llvm_emit_vertex(
const struct lp_build_tgsi_action *action,
@@ -2434,7 +2428,6 @@ static void create_function(struct si_shader_context *si_shader_ctx)
default:
LLVMAddAttribute(P, LLVMInRegAttribute);
break;
#if HAVE_LLVM >= 0x0304
/* We tell llvm that array inputs are passed by value to allow Sinking pass
* to move load. Inputs are constant so this is fine. */
case SI_PARAM_CONST:
@@ -2442,11 +2435,9 @@ static void create_function(struct si_shader_context *si_shader_ctx)
case SI_PARAM_RESOURCE:
LLVMAddAttribute(P, LLVMByValAttribute);
break;
#endif
}
}
#if HAVE_LLVM >= 0x0304
if (bld_base->info &&
(bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
@@ -2455,7 +2446,6 @@ static void create_function(struct si_shader_context *si_shader_ctx)
LLVMArrayType(i32, 64),
"ddxy_lds",
LOCAL_ADDR_SPACE);
#endif
}
static void preload_constants(struct si_shader_context *si_shader_ctx)
@@ -2764,9 +2754,7 @@ int si_pipe_shader_create(
bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
#if HAVE_LLVM >= 0x0304
bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
#endif
bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
@@ -2775,10 +2763,8 @@ int si_pipe_shader_create(
bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
#if HAVE_LLVM >= 0x0304
bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
#endif
bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
src/gallium/drivers/radeonsi/si_state.c
+1 -19
View File
@@ -1485,9 +1485,6 @@ boolean si_is_format_supported(struct pipe_screen *screen,
return FALSE;
if (sample_count > 1) {
if (HAVE_LLVM < 0x0304)
return FALSE;
/* 2D tiling on CIK is supported since DRM 2.35.0 */
if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
return FALSE;
@@ -2239,16 +2236,12 @@ static void *si_create_fs_state(struct pipe_context *ctx,
return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
}
#if LLVM_SUPPORTS_GEOM_SHADERS
static void *si_create_gs_state(struct pipe_context *ctx,
const struct pipe_shader_state *state)
{
return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
}
#endif
static void *si_create_vs_state(struct pipe_context *ctx,
const struct pipe_shader_state *state)
{
@@ -2269,8 +2262,6 @@ static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
sctx->vs_shader = sel;
}
#if LLVM_SUPPORTS_GEOM_SHADERS
static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
{
struct si_context *sctx = (struct si_context *)ctx;
@@ -2282,8 +2273,6 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
sctx->gs_shader = sel;
}
#endif
static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
{
struct si_context *sctx = (struct si_context *)ctx;
@@ -2337,8 +2326,6 @@ static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
si_delete_shader_selector(ctx, sel);
}
#if LLVM_SUPPORTS_GEOM_SHADERS
static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
{
struct si_context *sctx = (struct si_context *)ctx;
@@ -2351,8 +2338,6 @@ static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
si_delete_shader_selector(ctx, sel);
}
#endif
static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
{
struct si_context *sctx = (struct si_context *)ctx;
@@ -2835,11 +2820,9 @@ static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count,
si_set_sampler_states(sctx, pm4, count, states,
&sctx->samplers[PIPE_SHADER_VERTEX],
R_00B130_SPI_SHADER_USER_DATA_VS_0);
#if LLVM_SUPPORTS_GEOM_SHADERS
si_set_sampler_states(sctx, pm4, count, states,
&sctx->samplers[PIPE_SHADER_VERTEX],
R_00B330_SPI_SHADER_USER_DATA_ES_0);
#endif
si_pm4_set_state(sctx, vs_sampler, pm4);
}
@@ -3067,11 +3050,10 @@ void si_init_state_functions(struct si_context *sctx)
sctx->b.b.bind_fs_state = si_bind_ps_shader;
sctx->b.b.delete_vs_state = si_delete_vs_shader;
sctx->b.b.delete_fs_state = si_delete_ps_shader;
#if LLVM_SUPPORTS_GEOM_SHADERS
sctx->b.b.create_gs_state = si_create_gs_state;
sctx->b.b.bind_gs_state = si_bind_gs_shader;
sctx->b.b.delete_gs_state = si_delete_gs_shader;
#endif
sctx->b.b.create_sampler_state = si_create_sampler_state;
sctx->b.b.bind_sampler_states = si_bind_sampler_states;