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r600g: remove dead code after the rework

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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák
2012-04-02 00:33:52 +02:00
parent 68bbfc1afe
commit a633d82ce3
5 changed files with 8 additions and 125 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/r600/evergreen_state.c
-38
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@@ -2807,41 +2807,3 @@ void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
/* Don't set the 'is_flush' flag in r600_pipe_dsa, evergreen doesn't need it. */
return rstate;
}
void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
struct r600_pipe_resource_state *rstate)
{
rstate->id = R600_PIPE_STATE_RESOURCE;
rstate->val[0] = 0;
rstate->bo[0] = NULL;
rstate->val[1] = 0;
rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
rstate->val[4] = 0;
rstate->val[5] = 0;
rstate->val[6] = 0;
rstate->val[7] = 0xc0000000;
}
void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
struct r600_pipe_resource_state *rstate,
struct r600_resource *rbuffer,
unsigned offset, unsigned stride,
enum radeon_bo_usage usage)
{
uint64_t va;
va = r600_resource_va(ctx->screen, (void *)rbuffer);
rstate->bo[0] = rbuffer;
rstate->bo_usage[0] = usage;
rstate->val[0] = (offset + va) & 0xFFFFFFFFUL;
rstate->val[1] = rbuffer->buf->size - offset - 1;
rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
S_030008_STRIDE(stride) |
(((va + offset) >> 32UL) & 0xFF);
}
src/gallium/drivers/r600/r600.h
-12
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@@ -128,8 +128,6 @@ struct r600_pipe_resource_state {
#define R600_BLOCK_STATUS_DIRTY (1 << 1)
#define R600_BLOCK_STATUS_RESOURCE_DIRTY (1 << 2)
#define R600_BLOCK_STATUS_RESOURCE_VERTEX (1 << 3)
struct r600_block_reloc {
struct r600_resource *bo;
enum radeon_bo_usage bo_usage;
@@ -245,14 +243,4 @@ static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
state->nregs++;
}
static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
uint32_t value, struct r600_resource *bo,
enum radeon_bo_usage usage)
{
state->regs[state->nregs].value = value;
state->regs[state->nregs].bo = bo;
state->regs[state->nregs].bo_usage = usage;
state->nregs++;
}
#endif
src/gallium/drivers/r600/r600_hw_context.c
+8 -34
View File
@@ -890,7 +890,6 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_
{
int dirty;
int num_regs = ctx->chip_class >= EVERGREEN ? 8 : 7;
boolean is_vertex;
if (state == NULL) {
block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
@@ -901,7 +900,6 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_
return;
}
is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
if (memcmp(block->reg, state->val, num_regs*4)) {
@@ -914,37 +912,18 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_
dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
if (!dirty) {
if (is_vertex) {
if (block->reloc[1].bo->buf != state->bo[0]->buf)
dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
} else {
if ((block->reloc[1].bo->buf != state->bo[0]->buf) ||
(block->reloc[2].bo->buf != state->bo[1]->buf))
dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
}
if ((block->reloc[1].bo->buf != state->bo[0]->buf) ||
(block->reloc[2].bo->buf != state->bo[1]->buf))
dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
}
if (dirty) {
if (is_vertex) {
/* VERTEX RESOURCE, we preted there is 2 bo to relocate so
* we have single case btw VERTEX & TEXTURE resource
*/
pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
block->reloc[1].bo_usage = state->bo_usage[0];
pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
} else {
/* TEXTURE RESOURCE */
pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
block->reloc[1].bo_usage = state->bo_usage[0];
pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b.b);
block->reloc[2].bo_usage = state->bo_usage[1];
}
/* TEXTURE RESOURCE */
pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
block->reloc[1].bo_usage = state->bo_usage[0];
pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b.b);
block->reloc[2].bo_usage = state->bo_usage[1];
if (is_vertex)
block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
else
block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
}
}
@@ -1106,11 +1085,6 @@ void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r60
int cp_dwords = block->pm4_ndwords;
int nbo = block->nbo;
if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
nbo = 1;
cp_dwords -= 2; /* don't copy the second NOP */
}
for (int j = 0; j < nbo; j++) {
if (block->pm4_bo_index[j]) {
/* find relocation */
src/gallium/drivers/r600/r600_pipe.h
-13
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@@ -376,13 +376,6 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader
void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
void evergreen_polygon_offset_update(struct r600_context *rctx);
void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
struct r600_pipe_resource_state *rstate);
void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
struct r600_pipe_resource_state *rstate,
struct r600_resource *rbuffer,
unsigned offset, unsigned stride,
enum radeon_bo_usage usage);
boolean evergreen_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
@@ -440,12 +433,6 @@ void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shad
void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
void *r600_create_db_flush_dsa(struct r600_context *rctx);
void r600_polygon_offset_update(struct r600_context *rctx);
void r600_pipe_init_buffer_resource(struct r600_context *rctx,
struct r600_pipe_resource_state *rstate);
void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
struct r600_resource *rbuffer,
unsigned offset, unsigned stride,
enum radeon_bo_usage usage);
void r600_adjust_gprs(struct r600_context *rctx);
boolean r600_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
src/gallium/drivers/r600/r600_state.c
-28
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@@ -2435,31 +2435,3 @@ void *r600_create_db_flush_dsa(struct r600_context *rctx)
dsa_state->is_flush = true;
return rstate;
}
void r600_pipe_init_buffer_resource(struct r600_context *rctx,
struct r600_pipe_resource_state *rstate)
{
rstate->id = R600_PIPE_STATE_RESOURCE;
rstate->bo[0] = NULL;
rstate->val[0] = 0;
rstate->val[1] = 0;
rstate->val[2] = 0;
rstate->val[3] = 0;
rstate->val[4] = 0;
rstate->val[5] = 0;
rstate->val[6] = 0xc0000000;
}
void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
struct r600_resource *rbuffer,
unsigned offset, unsigned stride,
enum radeon_bo_usage usage)
{
rstate->val[0] = offset;
rstate->bo[0] = rbuffer;
rstate->bo_usage[0] = usage;
rstate->val[1] = rbuffer->buf->size - offset - 1;
rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
S_038008_STRIDE(stride);
}