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svga: assorted code clean-ups in svga drm code

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Fix whitespace/formatting.  Remove trailing whitespace.  Replace
tabs with spaces.  No functional change.

Signed-off-by: Brian Paul <brian.paul@broadcom.com>
Reviewed-by: Neha Bhende <neha.bhende@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35663>
This commit is contained in:
Brian Paul
2025-06-20 14:15:32 -06:00
committed by Marge Bot
parent d7d31708fa
commit a5b36600d8
16 changed files with 274 additions and 274 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/winsys/svga/drm/pb_buffer_simple_fenced.c
+37 -39
View File
@@ -150,7 +150,7 @@ fenced_manager_dump_locked(struct fenced_manager *fenced_mgr)
curr = fenced_mgr->unfenced.next;
next = curr->next;
while(curr != &fenced_mgr->unfenced) {
while (curr != &fenced_mgr->unfenced) {
fenced_buf = list_entry(curr, struct fenced_buffer, head);
assert(!fenced_buf->fence);
debug_printf("%10p %"PRIu64" %8u %7s\n",
@@ -164,7 +164,7 @@ fenced_manager_dump_locked(struct fenced_manager *fenced_mgr)
curr = fenced_mgr->fenced.next;
next = curr->next;
while(curr != &fenced_mgr->fenced) {
while (curr != &fenced_mgr->fenced) {
int signaled;
fenced_buf = list_entry(curr, struct fenced_buffer, head);
assert(fenced_buf->buffer);
@@ -284,7 +284,7 @@ fenced_buffer_finish_locked(struct fenced_manager *fenced_mgr,
assert(pipe_is_referenced(&fenced_buf->base.base.reference));
assert(fenced_buf->fence);
if(fenced_buf->fence) {
if (fenced_buf->fence) {
struct pipe_fence_handle *fence = NULL;
int finished;
bool proceed;
@@ -308,7 +308,7 @@ fenced_buffer_finish_locked(struct fenced_manager *fenced_mgr,
ops->fence_reference(ops, &fence, NULL);
if(proceed && finished == 0) {
if (proceed && finished == 0) {
/*
* Remove from the fenced list
*/
@@ -349,10 +349,10 @@ fenced_manager_check_signalled_locked(struct fenced_manager *fenced_mgr,
curr = fenced_mgr->fenced.next;
next = curr->next;
while(curr != &fenced_mgr->fenced) {
while (curr != &fenced_mgr->fenced) {
fenced_buf = list_entry(curr, struct fenced_buffer, head);
if(fenced_buf->fence != prev_fence) {
if (fenced_buf->fence != prev_fence) {
int signaled;
if (wait) {
@@ -364,8 +364,7 @@ fenced_manager_check_signalled_locked(struct fenced_manager *fenced_mgr,
* without further waits.
*/
wait = false;
}
else {
} else {
signaled = ops->fence_signalled(ops, fenced_buf->fence, 0);
}
@@ -374,8 +373,7 @@ fenced_manager_check_signalled_locked(struct fenced_manager *fenced_mgr,
}
prev_fence = fenced_buf->fence;
}
else {
} else {
/* This buffer's fence object is identical to the previous buffer's
* fence object, so no need to check the fence again.
*/
@@ -400,7 +398,7 @@ fenced_manager_check_signalled_locked(struct fenced_manager *fenced_mgr,
static void
fenced_buffer_destroy_gpu_storage_locked(struct fenced_buffer *fenced_buf)
{
if(fenced_buf->buffer) {
if (fenced_buf->buffer) {
pb_reference(&fenced_buf->buffer, NULL);
}
}
@@ -450,26 +448,26 @@ fenced_buffer_create_gpu_storage_locked(struct fenced_manager *fenced_mgr,
* - fences are expiring,
* - or buffers are being being swapped out from GPU memory into CPU memory.
*/
while(!fenced_buf->buffer &&
while (!fenced_buf->buffer &&
(fenced_manager_check_signalled_locked(fenced_mgr, false))) {
fenced_buffer_try_create_gpu_storage_locked(fenced_mgr, fenced_buf,
desc);
}
if(!fenced_buf->buffer && wait) {
if (!fenced_buf->buffer && wait) {
/*
* Same as before, but this time around, wait to free buffers if
* necessary.
*/
while(!fenced_buf->buffer &&
while (!fenced_buf->buffer &&
(fenced_manager_check_signalled_locked(fenced_mgr, true))) {
fenced_buffer_try_create_gpu_storage_locked(fenced_mgr, fenced_buf,
desc);
}
}
if(!fenced_buf->buffer) {
if(0)
if (!fenced_buf->buffer) {
if (0)
fenced_manager_dump_locked(fenced_mgr);
/* give up */
@@ -512,7 +510,7 @@ fenced_buffer_map(struct pb_buffer *buf,
/*
* Serialize writes.
*/
while((fenced_buf->flags & PB_USAGE_GPU_WRITE) ||
while ((fenced_buf->flags & PB_USAGE_GPU_WRITE) ||
((fenced_buf->flags & PB_USAGE_GPU_READ) &&
(flags & PB_USAGE_CPU_WRITE))) {
@@ -520,7 +518,7 @@ fenced_buffer_map(struct pb_buffer *buf,
* Don't wait for the GPU to finish accessing it,
* if blocking is forbidden.
*/
if((flags & PB_USAGE_DONTBLOCK) &&
if ((flags & PB_USAGE_DONTBLOCK) &&
ops->fence_signalled(ops, fenced_buf->fence, 0) != 0) {
goto done;
}
@@ -538,7 +536,7 @@ fenced_buffer_map(struct pb_buffer *buf,
map = pb_map(fenced_buf->buffer, flags, flush_ctx);
if(map) {
if (map) {
++fenced_buf->mapcount;
fenced_buf->flags |= flags & PB_USAGE_CPU_READ_WRITE;
}
@@ -559,11 +557,11 @@ fenced_buffer_unmap(struct pb_buffer *buf)
mtx_lock(&fenced_mgr->mutex);
assert(fenced_buf->mapcount);
if(fenced_buf->mapcount) {
if (fenced_buf->mapcount) {
if (fenced_buf->buffer)
pb_unmap(fenced_buf->buffer);
--fenced_buf->mapcount;
if(!fenced_buf->mapcount)
if (!fenced_buf->mapcount)
fenced_buf->flags &= ~PB_USAGE_CPU_READ_WRITE;
}
@@ -582,7 +580,7 @@ fenced_buffer_validate(struct pb_buffer *buf,
mtx_lock(&fenced_mgr->mutex);
if(!vl) {
if (!vl) {
/* invalidate */
fenced_buf->vl = NULL;
fenced_buf->validation_flags = 0;
@@ -595,12 +593,12 @@ fenced_buffer_validate(struct pb_buffer *buf,
flags &= PB_USAGE_GPU_READ_WRITE;
/* Buffer cannot be validated in two different lists */
if(fenced_buf->vl && fenced_buf->vl != vl) {
if (fenced_buf->vl && fenced_buf->vl != vl) {
ret = PIPE_ERROR_RETRY;
goto done;
}
if(fenced_buf->vl == vl &&
if (fenced_buf->vl == vl &&
(fenced_buf->validation_flags & flags) == flags) {
/* Nothing to do -- buffer already validated */
ret = PIPE_OK;
@@ -634,7 +632,7 @@ fenced_buffer_fence(struct pb_buffer *buf,
assert(pipe_is_referenced(&fenced_buf->base.base.reference));
assert(fenced_buf->buffer);
if(fence != fenced_buf->fence) {
if (fence != fenced_buf->fence) {
assert(fenced_buf->vl);
assert(fenced_buf->validation_flags);
@@ -672,9 +670,9 @@ fenced_buffer_get_base_buffer(struct pb_buffer *buf,
assert(fenced_buf->buffer);
if(fenced_buf->buffer)
if (fenced_buf->buffer) {
pb_get_base_buffer(fenced_buf->buffer, base_buf, offset);
else {
} else {
*base_buf = buf;
*offset = 0;
}
@@ -685,12 +683,12 @@ fenced_buffer_get_base_buffer(struct pb_buffer *buf,
static const struct pb_vtbl
fenced_buffer_vtbl = {
fenced_buffer_destroy,
fenced_buffer_map,
fenced_buffer_unmap,
fenced_buffer_validate,
fenced_buffer_fence,
fenced_buffer_get_base_buffer
fenced_buffer_destroy,
fenced_buffer_map,
fenced_buffer_unmap,
fenced_buffer_validate,
fenced_buffer_fence,
fenced_buffer_get_base_buffer
};
@@ -707,7 +705,7 @@ fenced_bufmgr_create_buffer(struct pb_manager *mgr,
enum pipe_error ret;
fenced_buf = CALLOC_STRUCT(fenced_buffer);
if(!fenced_buf)
if (!fenced_buf)
goto no_buffer;
pipe_reference_init(&fenced_buf->base.base.reference, 1);
@@ -730,7 +728,7 @@ fenced_bufmgr_create_buffer(struct pb_manager *mgr,
/*
* Give up.
*/
if(ret != PIPE_OK) {
if (ret != PIPE_OK) {
goto no_storage;
}
@@ -756,12 +754,12 @@ fenced_bufmgr_flush(struct pb_manager *mgr)
struct fenced_manager *fenced_mgr = fenced_manager(mgr);
mtx_lock(&fenced_mgr->mutex);
while(fenced_manager_check_signalled_locked(fenced_mgr, true))
while (fenced_manager_check_signalled_locked(fenced_mgr, true))
;
mtx_unlock(&fenced_mgr->mutex);
assert(fenced_mgr->provider->flush);
if(fenced_mgr->provider->flush)
if (fenced_mgr->provider->flush)
fenced_mgr->provider->flush(fenced_mgr->provider);
}
@@ -780,7 +778,7 @@ fenced_bufmgr_destroy(struct pb_manager *mgr)
sched_yield();
#endif
mtx_lock(&fenced_mgr->mutex);
while(fenced_manager_check_signalled_locked(fenced_mgr, true))
while (fenced_manager_check_signalled_locked(fenced_mgr, true))
;
}
@@ -801,7 +799,7 @@ simple_fenced_bufmgr_create(struct pb_manager *provider,
{
struct fenced_manager *fenced_mgr;
if(!provider)
if (!provider)
return NULL;
fenced_mgr = CALLOC_STRUCT(fenced_manager);
src/gallium/winsys/svga/drm/vmw_buffer.c
+22 -21
View File
@@ -8,14 +8,14 @@
/**
* @file
* SVGA buffer manager for DMA buffers.
*
*
* DMA buffers are used for pixel and vertex data upload/download to/from
* the virtual SVGA hardware.
*
* This file implements a pipebuffer library's buffer manager, so that we can
* use pipepbuffer's suballocation, fencing, and debugging facilities with
* DMA buffers.
*
*
* @author Jose Fonseca <jfonseca@vmware.com>
*/
@@ -38,9 +38,9 @@ struct vmw_dma_bufmgr;
struct vmw_dma_buffer
{
struct pb_buffer base;
struct vmw_dma_bufmgr *mgr;
struct vmw_region *region;
void *map;
unsigned map_flags;
@@ -63,7 +63,7 @@ vmw_pb_to_dma_buffer(struct pb_buffer *buf)
struct vmw_dma_bufmgr
{
struct pb_manager base;
struct vmw_winsys_screen *vws;
};
@@ -173,7 +173,8 @@ vmw_dma_buffer_fence( struct pb_buffer *_buf,
struct pipe_fence_handle *fence )
{
/* We don't need to do anything, as the pipebuffer library
* will take care of delaying the destruction of fenced buffers */
* will take care of delaying the destruction of fenced buffers
*/
}
@@ -197,9 +198,9 @@ vmw_dma_bufmgr_create_buffer(struct pb_manager *_mgr,
struct vmw_dma_buffer *buf;
const struct vmw_buffer_desc *desc =
(const struct vmw_buffer_desc *) pb_desc;
buf = CALLOC_STRUCT(vmw_dma_buffer);
if(!buf)
if (!buf)
goto error1;
pipe_reference_init(&buf->base.base.reference, 1);
@@ -212,10 +213,10 @@ vmw_dma_bufmgr_create_buffer(struct pb_manager *_mgr,
buf->region = desc->region;
} else {
buf->region = vmw_ioctl_region_create(vws, size);
if(!buf->region)
goto error2;
if (!buf->region)
goto error2;
}
return &buf->base;
error2:
FREE(buf);
@@ -243,17 +244,17 @@ struct pb_manager *
vmw_dma_bufmgr_create(struct vmw_winsys_screen *vws)
{
struct vmw_dma_bufmgr *mgr;
mgr = CALLOC_STRUCT(vmw_dma_bufmgr);
if(!mgr)
if (!mgr)
return NULL;
mgr->base.destroy = vmw_dma_bufmgr_destroy;
mgr->base.create_buffer = vmw_dma_bufmgr_create_buffer;
mgr->base.flush = vmw_dma_bufmgr_flush;
mgr->vws = vws;
return &mgr->base;
}
@@ -265,17 +266,17 @@ vmw_dma_bufmgr_region_ptr(struct pb_buffer *buf,
struct pb_buffer *base_buf;
pb_size offset = 0;
struct vmw_dma_buffer *dma_buf;
pb_get_base_buffer( buf, &base_buf, &offset );
dma_buf = vmw_pb_to_dma_buffer(base_buf);
if(!dma_buf)
if (!dma_buf)
return false;
*ptr = vmw_ioctl_region_ptr(dma_buf->region);
ptr->offset += offset;
return true;
}
src/gallium/winsys/svga/drm/vmw_context.c
+49 -48
View File
@@ -58,11 +58,11 @@ struct vmw_buffer_relocation
union {
struct {
struct SVGAGuestPtr *where;
struct SVGAGuestPtr *where;
} region;
struct {
SVGAMobId *id;
uint32 *offset_into_mob;
SVGAMobId *id;
uint32 *offset_into_mob;
} mob;
};
};
@@ -102,7 +102,7 @@ struct vmw_svga_winsys_context
uint32_t staged;
uint32_t reserved;
} surface;
struct {
struct vmw_buffer_relocation relocs[VMW_REGION_RELOCS];
uint32_t size;
@@ -200,28 +200,29 @@ vmw_swc_flush(struct svga_winsys_context *swc,
}
assert(ret == PIPE_OK);
if(ret == PIPE_OK) {
if (ret == PIPE_OK) {
/* Apply relocations */
for(i = 0; i < vswc->region.used; ++i) {
for (i = 0; i < vswc->region.used; ++i) {
struct vmw_buffer_relocation *reloc = &vswc->region.relocs[i];
struct SVGAGuestPtr ptr;
if(!vmw_dma_bufmgr_region_ptr(reloc->buffer, &ptr))
if (!vmw_dma_bufmgr_region_ptr(reloc->buffer, &ptr))
assert(0);
ptr.offset += reloc->offset;
if (reloc->is_mob) {
if (reloc->mob.id)
*reloc->mob.id = ptr.gmrId;
if (reloc->mob.offset_into_mob)
*reloc->mob.offset_into_mob = ptr.offset;
else {
assert(ptr.offset == 0);
}
} else
*reloc->region.where = ptr;
if (reloc->is_mob) {
if (reloc->mob.id) {
*reloc->mob.id = ptr.gmrId;
}
if (reloc->mob.offset_into_mob) {
*reloc->mob.offset_into_mob = ptr.offset;
} else {
assert(ptr.offset == 0);
}
} else {
*reloc->region.where = ptr;
}
}
if (vswc->command.used || pfence != NULL)
@@ -243,7 +244,7 @@ vmw_swc_flush(struct svga_winsys_context *swc,
vswc->command.used = 0;
vswc->command.reserved = 0;
for(i = 0; i < vswc->surface.used + vswc->surface.staged; ++i) {
for (i = 0; i < vswc->surface.used + vswc->surface.staged; ++i) {
struct vmw_ctx_validate_item *isurf = &vswc->surface.items[i];
if (isurf->referenced)
p_atomic_dec(&isurf->vsurf->validated);
@@ -254,7 +255,7 @@ vmw_swc_flush(struct svga_winsys_context *swc,
vswc->surface.used = 0;
vswc->surface.reserved = 0;
for(i = 0; i < vswc->shader.used + vswc->shader.staged; ++i) {
for (i = 0; i < vswc->shader.used + vswc->shader.staged; ++i) {
struct vmw_ctx_validate_item *ishader = &vswc->shader.items[i];
if (ishader->referenced)
p_atomic_dec(&ishader->vshader->validated);
@@ -283,7 +284,7 @@ vmw_swc_flush(struct svga_winsys_context *swc,
vswc->base.imported_fence_fd = -1;
}
if(pfence)
if (pfence)
vmw_fence_reference(vswc->vws, pfence, fence);
vmw_fence_reference(vswc->vws, &fence, NULL);
@@ -300,7 +301,7 @@ vmw_swc_reserve(struct svga_winsys_context *swc,
#if MESA_DEBUG
/* Check if somebody forgot to check the previous failure */
if(vswc->must_flush) {
if (vswc->must_flush) {
debug_printf("Forgot to flush:\n");
debug_backtrace_dump(vswc->must_flush_stack, VMW_MUST_FLUSH_STACK);
assert(!vswc->must_flush);
@@ -309,10 +310,10 @@ vmw_swc_reserve(struct svga_winsys_context *swc,
#endif
assert(nr_bytes <= vswc->command.size);
if(nr_bytes > vswc->command.size)
if (nr_bytes > vswc->command.size)
return NULL;
if(vswc->preemptive_flush ||
if (vswc->preemptive_flush ||
vswc->command.used + nr_bytes > vswc->command.size ||
vswc->surface.used + nr_relocs > vswc->surface.size ||
vswc->shader.used + nr_relocs > vswc->shader.size ||
@@ -329,7 +330,7 @@ vmw_swc_reserve(struct svga_winsys_context *swc,
assert(vswc->surface.used + nr_relocs <= vswc->surface.size);
assert(vswc->shader.used + nr_relocs <= vswc->shader.size);
assert(vswc->region.used + nr_relocs <= vswc->region.size);
vswc->command.reserved = nr_bytes;
vswc->surface.reserved = nr_relocs;
vswc->surface.staged = 0;
@@ -337,7 +338,7 @@ vmw_swc_reserve(struct svga_winsys_context *swc,
vswc->shader.staged = 0;
vswc->region.reserved = nr_relocs;
vswc->region.staged = 0;
return vswc->command.buffer + vswc->command.used;
}
@@ -350,15 +351,15 @@ vmw_swc_get_command_buffer_size(struct svga_winsys_context *swc)
static void
vmw_swc_context_relocation(struct svga_winsys_context *swc,
uint32 *cid)
uint32 *cid)
{
*cid = swc->cid;
}
static bool
vmw_swc_add_validate_buffer(struct vmw_svga_winsys_context *vswc,
struct pb_buffer *pb_buf,
unsigned flags)
struct pb_buffer *pb_buf,
unsigned flags)
{
ASSERTED enum pipe_error ret;
unsigned translated_flags;
@@ -410,11 +411,11 @@ vmw_swc_region_relocation(struct svga_winsys_context *swc,
static void
vmw_swc_mob_relocation(struct svga_winsys_context *swc,
SVGAMobId *id,
uint32 *offset_into_mob,
struct svga_winsys_buffer *buffer,
uint32 offset,
unsigned flags)
SVGAMobId *id,
uint32 *offset_into_mob,
struct svga_winsys_buffer *buffer,
uint32 offset,
unsigned flags)
{
struct vmw_svga_winsys_context *vswc = vmw_svga_winsys_context(swc);
struct vmw_buffer_relocation *reloc;
@@ -480,9 +481,9 @@ vmw_swc_surface_clear_reference(struct svga_winsys_context *swc,
static void
vmw_swc_surface_only_relocation(struct svga_winsys_context *swc,
uint32 *where,
struct vmw_svga_winsys_surface *vsurf,
unsigned flags)
uint32 *where,
struct vmw_svga_winsys_surface *vsurf,
unsigned flags)
{
struct vmw_svga_winsys_context *vswc = vmw_svga_winsys_context(swc);
struct vmw_ctx_validate_item *isrf;
@@ -560,10 +561,10 @@ vmw_swc_surface_relocation(struct svga_winsys_context *swc,
static void
vmw_swc_shader_relocation(struct svga_winsys_context *swc,
uint32 *shid,
uint32 *mobid,
uint32 *offset,
struct svga_winsys_gb_shader *shader,
uint32 *shid,
uint32 *mobid,
uint32 *offset,
struct svga_winsys_gb_shader *shader,
unsigned flags)
{
struct vmw_svga_winsys_context *vswc = vmw_svga_winsys_context(swc);
@@ -571,7 +572,7 @@ vmw_swc_shader_relocation(struct svga_winsys_context *swc,
struct vmw_svga_winsys_shader *vshader;
struct vmw_ctx_validate_item *ishader;
if(!shader) {
if (!shader) {
*shid = SVGA3D_INVALID_ID;
return;
}
@@ -602,7 +603,7 @@ vmw_swc_shader_relocation(struct svga_winsys_context *swc,
if (vshader->buf)
vmw_swc_mob_relocation(swc, mobid, offset, vshader->buf,
0, SVGA_RELOC_READ);
0, SVGA_RELOC_READ);
}
static void
@@ -650,14 +651,14 @@ vmw_swc_destroy(struct svga_winsys_context *swc)
struct vmw_svga_winsys_context *vswc = vmw_svga_winsys_context(swc);
unsigned i;
for(i = 0; i < vswc->surface.used; ++i) {
for (i = 0; i < vswc->surface.used; ++i) {
struct vmw_ctx_validate_item *isurf = &vswc->surface.items[i];
if (isurf->referenced)
p_atomic_dec(&isurf->vsurf->validated);
vmw_svga_winsys_surface_reference(&isurf->vsurf, NULL);
}
for(i = 0; i < vswc->shader.used; ++i) {
for (i = 0; i < vswc->shader.used; ++i) {
struct vmw_ctx_validate_item *ishader = &vswc->shader.items[i];
if (ishader->referenced)
p_atomic_dec(&ishader->vshader->validated);
@@ -781,7 +782,7 @@ vmw_svga_winsys_context_create(struct svga_winsys_screen *sws)
struct vmw_svga_winsys_context *vswc;
vswc = CALLOC_STRUCT(vmw_svga_winsys_context);
if(!vswc)
if (!vswc)
return NULL;
vswc->base.destroy = vmw_swc_unref;
@@ -824,7 +825,7 @@ vmw_svga_winsys_context_create(struct svga_winsys_screen *sws)
vswc->region.size = VMW_REGION_RELOCS;
vswc->validate = pb_validate_create();
if(!vswc->validate)
if (!vswc->validate)
goto out_no_validate;
vswc->hash = util_hash_table_create_ptr_keys();
@@ -832,7 +833,7 @@ vmw_svga_winsys_context_create(struct svga_winsys_screen *sws)
goto out_no_hash;
if (vmw_has_userspace_surface(vws)) {
if(!(vswc->surface_id_bm = util_bitmask_create()))
if (!(vswc->surface_id_bm = util_bitmask_create()))
goto out_no_user_srf;
/**
* First id assigned is 0 which is invalid for surface id. Consume the
src/gallium/winsys/svga/drm/vmw_fence.c
+12 -12
View File
@@ -122,7 +122,7 @@ vmw_fences_signal(struct pb_fence_ops *fence_ops,
if (!has_emitted) {
emitted = ops->last_emitted;
if (emitted - signaled > (1 << 30))
emitted = signaled;
emitted = signaled;
}
if (signaled == ops->last_signaled && emitted == ops->last_emitted)
@@ -234,8 +234,8 @@ void vmw_fence_destroy(struct vmw_fence *vfence)
*/
void
vmw_fence_reference(struct vmw_winsys_screen *vws,
struct pipe_fence_handle **ptr,
struct pipe_fence_handle *fence)
struct pipe_fence_handle **ptr,
struct pipe_fence_handle *fence)
{
if (*ptr) {
struct vmw_fence *vfence = vmw_fence(*ptr);
@@ -277,8 +277,8 @@ vmw_fence_reference(struct vmw_winsys_screen *vws,
*/
int
vmw_fence_signalled(struct vmw_winsys_screen *vws,
struct pipe_fence_handle *fence,
unsigned flag)
struct pipe_fence_handle *fence,
unsigned flag)
{
struct vmw_fence *vfence;
int32_t vflags = SVGA_FENCE_FLAG_EXEC;
@@ -326,9 +326,9 @@ vmw_fence_signalled(struct vmw_winsys_screen *vws,
*/
int
vmw_fence_finish(struct vmw_winsys_screen *vws,
struct pipe_fence_handle *fence,
uint64_t timeout,
unsigned flag)
struct pipe_fence_handle *fence,
uint64_t timeout,
unsigned flag)
{
struct vmw_fence *vfence;
int32_t vflags = SVGA_FENCE_FLAG_EXEC;
@@ -361,8 +361,8 @@ vmw_fence_finish(struct vmw_winsys_screen *vws,
int32_t prev = old;
do {
old = prev;
prev = p_atomic_cmpxchg(&vfence->signalled, old, old | vflags);
old = prev;
prev = p_atomic_cmpxchg(&vfence->signalled, old, old | vflags);
} while (prev != old);
}
@@ -460,12 +460,12 @@ vmw_fence_ops_destroy(struct pb_fence_ops *ops)
* Returns NULL on failure.
*/
struct pb_fence_ops *
vmw_fence_ops_create(struct vmw_winsys_screen *vws)
vmw_fence_ops_create(struct vmw_winsys_screen *vws)
{
struct vmw_fence_ops *ops;
ops = CALLOC_STRUCT(vmw_fence_ops);
if(!ops)
if (!ops)
return NULL;
(void) mtx_init(&ops->mutex, mtx_plain);
src/gallium/winsys/svga/drm/vmw_fence.h
+10 -10
View File
@@ -20,29 +20,29 @@ struct vmw_winsys_screen;
struct pipe_fence_handle *
vmw_fence_create(struct pb_fence_ops *fence_ops,
uint32_t handle, uint32_t seqno, uint32_t mask, int32_t fd);
uint32_t handle, uint32_t seqno, uint32_t mask, int32_t fd);
int
vmw_fence_finish(struct vmw_winsys_screen *vws,
struct pipe_fence_handle *fence,
uint64_t timeout,
unsigned flag);
struct pipe_fence_handle *fence,
uint64_t timeout,
unsigned flag);
int
vmw_fence_get_fd(struct pipe_fence_handle *fence);
int
vmw_fence_signalled(struct vmw_winsys_screen *vws,
struct pipe_fence_handle *fence,
unsigned flag);
struct pipe_fence_handle *fence,
unsigned flag);
void
vmw_fence_reference(struct vmw_winsys_screen *vws,
struct pipe_fence_handle **ptr,
struct pipe_fence_handle *fence);
struct pipe_fence_handle **ptr,
struct pipe_fence_handle *fence);
struct pb_fence_ops *
vmw_fence_ops_create(struct vmw_winsys_screen *vws);
vmw_fence_ops_create(struct vmw_winsys_screen *vws);
#endif /* VMW_FENCE_H_ */
src/gallium/winsys/svga/drm/vmw_query.c
+1 -1
View File
@@ -116,7 +116,7 @@ vmw_svga_winsys_query_get_result(struct svga_winsys_screen *sws,
enum pipe_error
vmw_swc_query_bind(struct svga_winsys_context *swc,
vmw_swc_query_bind(struct svga_winsys_context *swc,
struct svga_winsys_gb_query *query,
unsigned flags)
{
src/gallium/winsys/svga/drm/vmw_query.h
+1 -1
View File
@@ -41,7 +41,7 @@ vmw_svga_winsys_query_get_result(struct svga_winsys_screen *sws,
void *result, uint32 resultLen);
enum pipe_error
vmw_swc_query_bind(struct svga_winsys_context *swc,
vmw_swc_query_bind(struct svga_winsys_context *swc,
struct svga_winsys_gb_query *query,
unsigned flags);
src/gallium/winsys/svga/drm/vmw_screen.c
+1 -1
View File
@@ -152,7 +152,7 @@ vmw_winsys_create( int fd )
if (!vws->fence_ops)
goto out_no_fence_ops;
if(!vmw_pools_init(vws))
if (!vmw_pools_init(vws))
goto out_no_pools;
if (!vmw_winsys_screen_init_svga(vws))
src/gallium/winsys/svga/drm/vmw_screen.h
+9 -9
View File
@@ -209,12 +209,12 @@ vmw_ioctl_fence_signalled(struct vmw_winsys_screen *vws,
void
vmw_ioctl_fence_unref(struct vmw_winsys_screen *vws,
uint32_t handle);
uint32_t handle);
uint32
vmw_ioctl_shader_create(struct vmw_winsys_screen *vws,
SVGA3dShaderType type,
uint32 code_len);
SVGA3dShaderType type,
uint32 code_len);
void
vmw_ioctl_shader_destroy(struct vmw_winsys_screen *vws, uint32 shid);
@@ -240,11 +240,11 @@ void vmw_pools_cleanup(struct vmw_winsys_screen *vws);
struct vmw_winsys_screen *vmw_winsys_create(int fd);
void vmw_winsys_destroy(struct vmw_winsys_screen *sws);
void vmw_winsys_screen_set_throttling(struct pipe_screen *screen,
uint32_t throttle_us);
uint32_t throttle_us);
struct pb_manager *
simple_fenced_bufmgr_create(struct pb_manager *provider,
struct pb_fence_ops *ops);
struct pb_fence_ops *ops);
void
vmw_fences_signal(struct pb_fence_ops *fence_ops,
uint32_t signaled,
@@ -253,12 +253,12 @@ vmw_fences_signal(struct pb_fence_ops *fence_ops,
struct svga_winsys_gb_shader *
vmw_svga_winsys_shader_create(struct svga_winsys_screen *sws,
SVGA3dShaderType type,
const uint32 *bytecode,
uint32 bytecodeLen);
SVGA3dShaderType type,
const uint32 *bytecode,
uint32 bytecodeLen);
void
vmw_svga_winsys_shader_destroy(struct svga_winsys_screen *sws,
struct svga_winsys_gb_shader *shader);
struct svga_winsys_gb_shader *shader);
size_t
vmw_svga_winsys_stats_len(void);
src/gallium/winsys/svga/drm/vmw_screen_dri.c
+32 -32
View File
@@ -33,8 +33,8 @@ struct dri1_api_version {
static struct svga_winsys_surface *
vmw_drm_surface_from_handle(struct svga_winsys_screen *sws,
struct winsys_handle *whandle,
SVGA3dSurfaceFormat *format);
struct winsys_handle *whandle,
SVGA3dSurfaceFormat *format);
static struct svga_winsys_surface *
vmw_drm_gb_surface_from_handle(struct svga_winsys_screen *sws,
@@ -42,18 +42,18 @@ vmw_drm_gb_surface_from_handle(struct svga_winsys_screen *sws,
SVGA3dSurfaceFormat *format);
static bool
vmw_drm_surface_get_handle(struct svga_winsys_screen *sws,
struct svga_winsys_surface *surface,
unsigned stride,
struct winsys_handle *whandle);
struct svga_winsys_surface *surface,
unsigned stride,
struct winsys_handle *whandle);
static struct dri1_api_version drm_required = { 2, 1, 0 };
static struct dri1_api_version drm_compat = { 2, 0, 0 };
static bool
vmw_dri1_check_version(const struct dri1_api_version *cur,
const struct dri1_api_version *required,
const struct dri1_api_version *compat,
const char component[])
const struct dri1_api_version *required,
const struct dri1_api_version *compat,
const char component[])
{
if (cur->major > required->major && cur->major <= compat->major)
return true;
@@ -89,7 +89,7 @@ svga_drm_winsys_screen_create(int fd)
drmFreeVersion(ver);
if (!vmw_dri1_check_version(&drm_ver, &drm_required,
&drm_compat, "vmwgfx drm driver"))
&drm_compat, "vmwgfx drm driver"))
return NULL;
vws = vmw_winsys_create(fd);
@@ -145,10 +145,10 @@ vmw_drm_gb_surface_from_handle(struct svga_winsys_screen *sws,
&mip_levels, &handle, &desc.region);
if (ret) {
fprintf(stderr, "Failed referencing shared surface. SID %d.\n"
"Error %d (%s).\n",
whandle->handle, ret, strerror(-ret));
return NULL;
fprintf(stderr, "Failed referencing shared surface. SID %d.\n"
"Error %d (%s).\n",
whandle->handle, ret, strerror(-ret));
return NULL;
}
if (mip_levels != 1) {
@@ -160,7 +160,7 @@ vmw_drm_gb_surface_from_handle(struct svga_winsys_screen *sws,
vsrf = CALLOC_STRUCT(vmw_svga_winsys_surface);
if (!vsrf)
goto out_mip;
goto out_mip;
pipe_reference_init(&vsrf->refcnt, 1);
p_atomic_set(&vsrf->validated, 0);
@@ -194,7 +194,7 @@ out_mip:
static struct svga_winsys_surface *
vmw_drm_surface_from_handle(struct svga_winsys_screen *sws,
struct winsys_handle *whandle,
SVGA3dSurfaceFormat *format)
SVGA3dSurfaceFormat *format)
{
struct vmw_svga_winsys_surface *vsrf;
struct svga_winsys_surface *ssrf;
@@ -223,9 +223,9 @@ vmw_drm_surface_from_handle(struct svga_winsys_screen *sws,
ret = drmPrimeFDToHandle(vws->ioctl.drm_fd, whandle->handle,
&handle);
if (ret) {
vmw_error("Failed to get handle from prime fd %d.\n",
(int) whandle->handle);
return NULL;
vmw_error("Failed to get handle from prime fd %d.\n",
(int) whandle->handle);
return NULL;
}
break;
default:
@@ -239,7 +239,7 @@ vmw_drm_surface_from_handle(struct svga_winsys_screen *sws,
rep->size_addr = (unsigned long)&size;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_REF_SURFACE,
&arg, sizeof(arg));
&arg, sizeof(arg));
/*
* Need to close the handle we got from prime.
@@ -262,21 +262,21 @@ vmw_drm_surface_from_handle(struct svga_winsys_screen *sws,
vmw_error("Incorrect number of mipmap levels on shared surface."
" SID %d, levels %d\n",
handle, rep->mip_levels[0]);
goto out_mip;
goto out_mip;
}
for (i=1; i < DRM_VMW_MAX_SURFACE_FACES; ++i) {
if (rep->mip_levels[i] != 0) {
if (rep->mip_levels[i] != 0) {
vmw_error("Incorrect number of faces levels on shared surface."
" SID %d, face %d present.\n",
handle, i);
goto out_mip;
}
goto out_mip;
}
}
vsrf = CALLOC_STRUCT(vmw_svga_winsys_surface);
if (!vsrf)
goto out_mip;
goto out_mip;
pipe_reference_init(&vsrf->refcnt, 1);
p_atomic_set(&vsrf->validated, 0);
@@ -304,16 +304,16 @@ out_mip:
static bool
vmw_drm_surface_get_handle(struct svga_winsys_screen *sws,
struct svga_winsys_surface *surface,
unsigned stride,
struct winsys_handle *whandle)
struct svga_winsys_surface *surface,
unsigned stride,
struct winsys_handle *whandle)
{
struct vmw_winsys_screen *vws = vmw_winsys_screen(sws);
struct vmw_svga_winsys_surface *vsrf;
int ret;
if (!surface)
return false;
return false;
vsrf = vmw_svga_winsys_surface(surface);
whandle->handle = vsrf->sid;
@@ -327,15 +327,15 @@ vmw_drm_surface_get_handle(struct svga_winsys_screen *sws,
break;
case WINSYS_HANDLE_TYPE_FD:
ret = drmPrimeHandleToFD(vws->ioctl.drm_fd, vsrf->sid, DRM_CLOEXEC,
(int *)&whandle->handle);
(int *)&whandle->handle);
if (ret) {
vmw_error("Failed to get file descriptor from prime.\n");
return false;
vmw_error("Failed to get file descriptor from prime.\n");
return false;
}
break;
default:
vmw_error("Attempt to export unsupported handle type %d.\n",
whandle->type);
whandle->type);
return false;
}
src/gallium/winsys/svga/drm/vmw_screen_ioctl.c
+74 -74
View File
@@ -71,7 +71,7 @@ vmw_ioctl_context_create(struct vmw_winsys_screen *vws)
VMW_FUNC;
ret = drmCommandRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_CONTEXT,
&c_arg, sizeof(c_arg));
&c_arg, sizeof(c_arg));
if (ret)
return -1;
@@ -112,7 +112,7 @@ vmw_ioctl_context_destroy(struct vmw_winsys_screen *vws, uint32 cid)
c_arg.cid = cid;
(void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_CONTEXT,
&c_arg, sizeof(c_arg));
&c_arg, sizeof(c_arg));
}
@@ -129,7 +129,7 @@ vmw_ioctl_surface_create(struct vmw_winsys_screen *vws,
struct drm_vmw_surface_create_req *req = &s_arg.req;
struct drm_vmw_surface_arg *rep = &s_arg.rep;
struct drm_vmw_size sizes[DRM_VMW_MAX_SURFACE_FACES*
DRM_VMW_MAX_MIP_LEVELS];
DRM_VMW_MAX_MIP_LEVELS];
struct drm_vmw_size *cur_size;
uint32_t iFace;
uint32_t iMipLevel;
@@ -144,20 +144,20 @@ vmw_ioctl_surface_create(struct vmw_winsys_screen *vws,
req->shareable = true;
assert(numFaces * numMipLevels < DRM_VMW_MAX_SURFACE_FACES*
DRM_VMW_MAX_MIP_LEVELS);
DRM_VMW_MAX_MIP_LEVELS);
cur_size = sizes;
for (iFace = 0; iFace < numFaces; ++iFace) {
SVGA3dSize mipSize = size;
req->mip_levels[iFace] = numMipLevels;
for (iMipLevel = 0; iMipLevel < numMipLevels; ++iMipLevel) {
cur_size->width = mipSize.width;
cur_size->height = mipSize.height;
cur_size->depth = mipSize.depth;
mipSize.width = MAX2(mipSize.width >> 1, 1);
mipSize.height = MAX2(mipSize.height >> 1, 1);
mipSize.depth = MAX2(mipSize.depth >> 1, 1);
cur_size++;
cur_size->width = mipSize.width;
cur_size->height = mipSize.height;
cur_size->depth = mipSize.depth;
mipSize.width = MAX2(mipSize.width >> 1, 1);
mipSize.height = MAX2(mipSize.height >> 1, 1);
mipSize.depth = MAX2(mipSize.depth >> 1, 1);
cur_size++;
}
}
for (iFace = numFaces; iFace < SVGA3D_MAX_SURFACE_FACES; ++iFace) {
@@ -167,7 +167,7 @@ vmw_ioctl_surface_create(struct vmw_winsys_screen *vws,
req->size_addr = (unsigned long)&sizes;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_SURFACE,
&s_arg, sizeof(s_arg));
&s_arg, sizeof(s_arg));
if (ret)
return -1;
@@ -243,7 +243,7 @@ vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
req->base.multisample_count = sampleCount;
} else {
assert(numFaces * numMipLevels < DRM_VMW_MAX_SURFACE_FACES*
DRM_VMW_MAX_MIP_LEVELS);
DRM_VMW_MAX_MIP_LEVELS);
req->base.array_size = 0;
}
@@ -281,7 +281,7 @@ vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
req->multisample_count = sampleCount;
} else {
assert(numFaces * numMipLevels < DRM_VMW_MAX_SURFACE_FACES*
DRM_VMW_MAX_MIP_LEVELS);
DRM_VMW_MAX_MIP_LEVELS);
req->array_size = 0;
}
@@ -289,7 +289,7 @@ vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
buffer_handle : SVGA3D_INVALID_ID;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_CREATE,
&s_arg.arg, sizeof(s_arg.arg));
&s_arg.arg, sizeof(s_arg.arg));
if (ret)
goto out_fail_create;
@@ -332,7 +332,7 @@ vmw_ioctl_surface_req(const struct vmw_winsys_screen *vws,
{
int ret;
switch(whandle->type) {
switch (whandle->type) {
case WINSYS_HANDLE_TYPE_SHARED:
case WINSYS_HANDLE_TYPE_KMS:
*needs_unref = false;
@@ -412,7 +412,7 @@ vmw_ioctl_gb_surface_ref(struct vmw_winsys_screen *vws,
*handle = req->sid;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_REF_EXT,
&s_arg, sizeof(s_arg));
&s_arg, sizeof(s_arg));
if (ret)
goto out_fail_ref;
@@ -440,7 +440,7 @@ vmw_ioctl_gb_surface_ref(struct vmw_winsys_screen *vws,
*handle = req->sid;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_REF,
&s_arg, sizeof(s_arg));
&s_arg, sizeof(s_arg));
if (ret)
goto out_fail_ref;
@@ -482,7 +482,7 @@ vmw_ioctl_surface_destroy(struct vmw_winsys_screen *vws, uint32 sid)
s_arg.sid = sid;
(void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_SURFACE,
&s_arg, sizeof(s_arg));
&s_arg, sizeof(s_arg));
}
void
@@ -550,7 +550,7 @@ vmw_ioctl_command(struct vmw_winsys_screen *vws, int32_t cid,
ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_EXECBUF, &arg, argsize);
if (ret == -EBUSY)
usleep(1000);
} while(ret == -ERESTART || ret == -EBUSY);
} while (ret == -ERESTART || ret == -EBUSY);
if (ret) {
vmw_error("%s error %s.\n", __func__, strerror(-ret));
abort();
@@ -562,7 +562,7 @@ vmw_ioctl_command(struct vmw_winsys_screen *vws, int32_t cid,
* Kernel has already synced, or caller requested no fence.
*/
if (pfence)
*pfence = NULL;
*pfence = NULL;
} else {
if (pfence) {
vmw_fences_signal(vws->fence_ops, rep.passed_seqno, rep.seqno,
@@ -606,7 +606,7 @@ vmw_ioctl_region_create(struct vmw_winsys_screen *vws, uint32_t size)
req->size = size;
do {
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_ALLOC_DMABUF, &arg,
sizeof(arg));
sizeof(arg));
} while (ret == -ERESTART);
if (ret) {
@@ -668,10 +668,10 @@ vmw_ioctl_region_map(struct vmw_region *region)
if (region->data == NULL) {
map = os_mmap(NULL, region->size, PROT_READ | PROT_WRITE, MAP_SHARED,
region->drm_fd, region->map_handle);
region->drm_fd, region->map_handle);
if (map == MAP_FAILED) {
vmw_error("%s: Map failed.\n", __func__);
return NULL;
vmw_error("%s: Map failed.\n", __func__);
return NULL;
}
// MADV_HUGEPAGE only exists on Linux
@@ -772,16 +772,16 @@ vmw_ioctl_releasefromcpu(struct vmw_region *region,
void
vmw_ioctl_fence_unref(struct vmw_winsys_screen *vws,
uint32_t handle)
uint32_t handle)
{
struct drm_vmw_fence_arg arg;
int ret;
memset(&arg, 0, sizeof(arg));
arg.handle = handle;
ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_FENCE_UNREF,
&arg, sizeof(arg));
&arg, sizeof(arg));
if (ret != 0)
vmw_error("%s Failed\n", __func__);
}
@@ -792,9 +792,9 @@ vmw_drm_fence_flags(uint32_t flags)
uint32_t dflags = 0;
if (flags & SVGA_FENCE_FLAG_EXEC)
dflags |= DRM_VMW_FENCE_FLAG_EXEC;
dflags |= DRM_VMW_FENCE_FLAG_EXEC;
if (flags & SVGA_FENCE_FLAG_QUERY)
dflags |= DRM_VMW_FENCE_FLAG_QUERY;
dflags |= DRM_VMW_FENCE_FLAG_QUERY;
return dflags;
}
@@ -802,8 +802,8 @@ vmw_drm_fence_flags(uint32_t flags)
int
vmw_ioctl_fence_signalled(struct vmw_winsys_screen *vws,
uint32_t handle,
uint32_t flags)
uint32_t handle,
uint32_t flags)
{
struct drm_vmw_fence_signaled_arg arg;
uint32_t vflags = vmw_drm_fence_flags(flags);
@@ -814,7 +814,7 @@ vmw_ioctl_fence_signalled(struct vmw_winsys_screen *vws,
arg.flags = vflags;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_SIGNALED,
&arg, sizeof(arg));
&arg, sizeof(arg));
if (ret != 0)
return ret;
@@ -829,7 +829,7 @@ vmw_ioctl_fence_signalled(struct vmw_winsys_screen *vws,
int
vmw_ioctl_fence_finish(struct vmw_winsys_screen *vws,
uint32_t handle,
uint32_t flags)
uint32_t flags)
{
struct drm_vmw_fence_wait_arg arg;
uint32_t vflags = vmw_drm_fence_flags(flags);
@@ -843,18 +843,18 @@ vmw_ioctl_fence_finish(struct vmw_winsys_screen *vws,
arg.flags = vflags;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_WAIT,
&arg, sizeof(arg));
&arg, sizeof(arg));
if (ret != 0)
vmw_error("%s Failed\n", __func__);
return 0;
}
uint32
vmw_ioctl_shader_create(struct vmw_winsys_screen *vws,
SVGA3dShaderType type,
uint32 code_len)
SVGA3dShaderType type,
uint32 code_len)
{
struct drm_vmw_shader_create_arg sh_arg;
int ret;
@@ -879,7 +879,7 @@ vmw_ioctl_shader_create(struct vmw_winsys_screen *vws,
}
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_SHADER,
&sh_arg, sizeof(sh_arg));
&sh_arg, sizeof(sh_arg));
if (ret)
return SVGA3D_INVALID_ID;
@@ -898,25 +898,25 @@ vmw_ioctl_shader_destroy(struct vmw_winsys_screen *vws, uint32 shid)
sh_arg.handle = shid;
(void)drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_UNREF_SHADER,
&sh_arg, sizeof(sh_arg));
&sh_arg, sizeof(sh_arg));
}
struct svga_3d_compat_cap {
SVGA3dFifoCapsRecordHeader header;
SVGA3dFifoCapPair pairs[SVGA3D_DEVCAP_MAX];
SVGA3dFifoCapsRecordHeader header;
SVGA3dFifoCapPair pairs[SVGA3D_DEVCAP_MAX];
};
static int
vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws,
const uint32_t *cap_buffer)
const uint32_t *cap_buffer)
{
int i;
if (vws->base.have_gb_objects) {
for (i = 0; i < vws->ioctl.num_cap_3d; ++i) {
vws->ioctl.cap_3d[i].has_cap = true;
vws->ioctl.cap_3d[i].result.u = cap_buffer[i];
vws->ioctl.cap_3d[i].has_cap = true;
vws->ioctl.cap_3d[i].result.u = cap_buffer[i];
}
return 0;
} else {
@@ -931,34 +931,34 @@ vmw_ioctl_parse_caps(struct vmw_winsys_screen *vws,
*/
capsBlock = cap_buffer;
for (offset = 0; capsBlock[offset] != 0; offset += capsBlock[offset]) {
const struct svga_3d_compat_cap *record;
assert(offset < SVGA_FIFO_3D_CAPS_SIZE);
record = (const struct svga_3d_compat_cap *) (capsBlock + offset);
if ((record->header.type >= 0) &&
(record->header.type <= SVGA3D_DEVCAP_MAX) &&
(!capsRecord || (record->header.type > capsRecord->header.type))) {
capsRecord = record;
}
const struct svga_3d_compat_cap *record;
assert(offset < SVGA_FIFO_3D_CAPS_SIZE);
record = (const struct svga_3d_compat_cap *) (capsBlock + offset);
if ((record->header.type >= 0) &&
(record->header.type <= SVGA3D_DEVCAP_MAX) &&
(!capsRecord || (record->header.type > capsRecord->header.type))) {
capsRecord = record;
}
}
if(!capsRecord)
return -1;
if (!capsRecord)
return -1;
/*
* Calculate the number of caps from the size of the record.
*/
capArray = (const SVGA3dFifoCapPair *) capsRecord->pairs;
numCaps = (int) ((capsRecord->header.length * sizeof(uint32) -
sizeof capsRecord->header) / (2 * sizeof(uint32)));
sizeof capsRecord->header) / (2 * sizeof(uint32)));
for (i = 0; i < numCaps; i++) {
index = capArray[i][0];
if (index < vws->ioctl.num_cap_3d) {
vws->ioctl.cap_3d[index].has_cap = true;
vws->ioctl.cap_3d[index].result.u = capArray[i][1];
} else {
debug_printf("Unknown devcaps seen: %d\n", index);
}
index = capArray[i][0];
if (index < vws->ioctl.num_cap_3d) {
vws->ioctl.cap_3d[index].has_cap = true;
vws->ioctl.cap_3d[index].result.u = capArray[i][1];
} else {
debug_printf("Unknown devcaps seen: %d\n", index);
}
}
}
return 0;
@@ -1009,7 +1009,7 @@ vmw_ioctl_init(struct vmw_winsys_screen *vws)
memset(&gp_arg, 0, sizeof(gp_arg));
gp_arg.param = DRM_VMW_PARAM_3D;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
&gp_arg, sizeof(gp_arg));
&gp_arg, sizeof(gp_arg));
if (ret || gp_arg.value == 0) {
vmw_error("No 3D enabled (%i, %s).\n", ret, strerror(-ret));
goto out_no_3d;
@@ -1018,7 +1018,7 @@ vmw_ioctl_init(struct vmw_winsys_screen *vws)
memset(&gp_arg, 0, sizeof(gp_arg));
gp_arg.param = DRM_VMW_PARAM_FIFO_HW_VERSION;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
&gp_arg, sizeof(gp_arg));
&gp_arg, sizeof(gp_arg));
if (ret) {
vmw_error("Failed to get fifo hw version (%i, %s).\n",
ret, strerror(-ret));
@@ -1206,8 +1206,8 @@ vmw_ioctl_init(struct vmw_winsys_screen *vws)
goto out_no_3d;
}
vws->ioctl.cap_3d = calloc(vws->ioctl.num_cap_3d,
sizeof(*vws->ioctl.cap_3d));
vws->ioctl.cap_3d = calloc(vws->ioctl.num_cap_3d,
sizeof(*vws->ioctl.cap_3d));
if (!vws->ioctl.cap_3d) {
debug_printf("Failed alloc fifo 3D caps buffer.\n");
goto out_no_caparray;
@@ -1223,18 +1223,18 @@ vmw_ioctl_init(struct vmw_winsys_screen *vws)
* driver sends the supported cap.
*/
ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_GET_3D_CAP,
&cap_arg, sizeof(cap_arg));
&cap_arg, sizeof(cap_arg));
if (ret) {
debug_printf("Failed to get 3D capabilities"
" (%i, %s).\n", ret, strerror(-ret));
" (%i, %s).\n", ret, strerror(-ret));
goto out_no_caps;
}
ret = vmw_ioctl_parse_caps(vws, cap_buffer);
if (ret) {
debug_printf("Failed to parse 3D capabilities"
" (%i, %s).\n", ret, strerror(-ret));
" (%i, %s).\n", ret, strerror(-ret));
goto out_no_caps;
}
@@ -1256,13 +1256,13 @@ vmw_ioctl_init(struct vmw_winsys_screen *vws)
drmFreeVersion(version);
vmw_printf("%s OK\n", __func__);
return true;
out_no_caps:
out_no_caps:
free(vws->ioctl.cap_3d);
out_no_caparray:
out_no_caparray:
free(cap_buffer);
out_no_3d:
out_no_3d:
drmFreeVersion(version);
out_no_version:
out_no_version:
vws->ioctl.num_cap_3d = 0;
debug_printf("%s Failed\n", __func__);
return false;
src/gallium/winsys/svga/drm/vmw_screen_pools.c
+6 -6
View File
@@ -74,7 +74,7 @@ vmw_query_pools_init(struct vmw_winsys_screen *vws)
vws->pools.query_fenced = simple_fenced_bufmgr_create(
vws->pools.query_mm, vws->fence_ops);
if(!vws->pools.query_fenced)
if (!vws->pools.query_fenced)
goto out_no_query_fenced;
return true;
@@ -104,7 +104,7 @@ vmw_pools_init(struct vmw_winsys_screen *vws)
vws->pools.dma_mm = mm_bufmgr_create(vws->pools.dma_base,
VMW_GMR_POOL_SIZE,
12 /* 4096 alignment */);
if(!vws->pools.dma_mm)
if (!vws->pools.dma_mm)
goto error;
vws->pools.dma_cache =
@@ -118,8 +118,8 @@ vmw_pools_init(struct vmw_winsys_screen *vws)
vws->pools.dma_fenced =
simple_fenced_bufmgr_create(vws->pools.dma_cache,
vws->fence_ops);
if(!vws->pools.dma_fenced)
if (!vws->pools.dma_fenced)
goto error;
/*
@@ -139,12 +139,12 @@ vmw_pools_init(struct vmw_winsys_screen *vws)
8192,
16384,
&desc);
if(!vws->pools.dma_slab)
if (!vws->pools.dma_slab)
goto error;
vws->pools.dma_slab_fenced =
simple_fenced_bufmgr_create(vws->pools.dma_slab,
vws->fence_ops);
vws->fence_ops);
if (!vws->pools.dma_slab_fenced)
goto error;
src/gallium/winsys/svga/drm/vmw_screen_svga.c
+14 -14
View File
@@ -363,7 +363,7 @@ vmw_svga_winsys_buffer_create(struct svga_winsys_screen *sws,
if (usage == SVGA_BUFFER_USAGE_PINNED) {
if (vws->pools.query_fenced == NULL && !vmw_query_pools_init(vws))
return NULL;
return NULL;
provider = vws->pools.query_fenced;
} else if (usage == SVGA_BUFFER_USAGE_SHADER) {
provider = vws->pools.dma_slab_fenced;
@@ -376,7 +376,7 @@ vmw_svga_winsys_buffer_create(struct svga_winsys_screen *sws,
assert(provider);
buffer = provider->create_buffer(provider, size, &desc.pb_desc);
if(!buffer && provider == vws->pools.dma_fenced) {
if (!buffer && provider == vws->pools.dma_fenced) {
assert(provider);
provider = vws->pools.dma_slab_fenced;
@@ -512,7 +512,7 @@ vmw_svga_winsys_surface_create(struct svga_winsys_screen *sws,
memset(&desc, 0, sizeof(desc));
surface = CALLOC_STRUCT(vmw_svga_winsys_surface);
if(!surface)
if (!surface)
goto no_surface;
pipe_reference_init(&surface->refcnt, 1);
@@ -615,7 +615,7 @@ vmw_svga_winsys_surface_create(struct svga_winsys_screen *sws,
surface->sid = vmw_ioctl_surface_create(vws, (SVGA3dSurface1Flags)flags,
format, usage, size, numLayers,
numMipLevels, sampleCount);
if(surface->sid == SVGA3D_INVALID_ID)
if (surface->sid == SVGA3D_INVALID_ID)
goto no_sid;
/* Best estimate for surface size, used for early flushing. */
@@ -652,7 +652,7 @@ vmw_svga_winsys_surface_can_create(struct svga_winsys_screen *sws,
buffer_size *= numSamples;
if (buffer_size > vws->ioctl.max_texture_size) {
return false;
return false;
}
return true;
}
@@ -669,8 +669,8 @@ vmw_svga_winsys_surface_is_flushed(struct svga_winsys_screen *sws,
static void
vmw_svga_winsys_surface_ref(struct svga_winsys_screen *sws,
struct svga_winsys_surface **pDst,
struct svga_winsys_surface *src)
struct svga_winsys_surface **pDst,
struct svga_winsys_surface *src)
{
struct vmw_svga_winsys_surface *d_vsurf = vmw_svga_winsys_surface(*pDst);
struct vmw_svga_winsys_surface *s_vsurf = vmw_svga_winsys_surface(src);
@@ -719,24 +719,24 @@ vmw_svga_winsys_get_cap(struct svga_winsys_screen *sws,
struct svga_winsys_gb_shader *
vmw_svga_winsys_shader_create(struct svga_winsys_screen *sws,
SVGA3dShaderType type,
const uint32 *bytecode,
uint32 bytecodeLen)
SVGA3dShaderType type,
const uint32 *bytecode,
uint32 bytecodeLen)
{
struct vmw_winsys_screen *vws = vmw_winsys_screen(sws);
struct vmw_svga_winsys_shader *shader;
void *code;
shader = CALLOC_STRUCT(vmw_svga_winsys_shader);
if(!shader)
if (!shader)
goto out_no_shader;
pipe_reference_init(&shader->refcnt, 1);
p_atomic_set(&shader->validated, 0);
shader->screen = vws;
shader->buf = vmw_svga_winsys_buffer_create(sws, 64,
SVGA_BUFFER_USAGE_SHADER,
bytecodeLen);
SVGA_BUFFER_USAGE_SHADER,
bytecodeLen);
if (!shader->buf)
goto out_no_buf;
@@ -765,7 +765,7 @@ out_no_shader:
void
vmw_svga_winsys_shader_destroy(struct svga_winsys_screen *sws,
struct svga_winsys_gb_shader *shader)
struct svga_winsys_gb_shader *shader)
{
struct vmw_svga_winsys_shader *d_shader =
vmw_svga_winsys_shader(shader);
src/gallium/winsys/svga/drm/vmw_shader.c
+1 -1
View File
@@ -23,7 +23,7 @@ vmw_svga_winsys_shader_reference(struct vmw_svga_winsys_shader **pdst,
struct pipe_reference *dst_ref;
struct vmw_svga_winsys_shader *dst;
if(pdst == NULL || *pdst == src)
if (pdst == NULL || *pdst == src)
return;
dst = *pdst;
src/gallium/winsys/svga/drm/vmw_surface.c
+4 -4
View File
@@ -79,7 +79,7 @@ out_unlock:
mtx_unlock(&vsrf->mutex);
}
void *
vmw_svga_winsys_surface_map(struct svga_winsys_context *swc,
struct svga_winsys_surface *srf,
@@ -144,7 +144,7 @@ vmw_svga_winsys_surface_map(struct svga_winsys_context *swc,
PIPE_MAP_DONTBLOCK | pb_flags);
if (data)
goto out_mapped;
}
}
/*
* Attempt to get a new buffer.
@@ -184,7 +184,7 @@ vmw_svga_winsys_surface_map(struct svga_winsys_context *swc,
* But tell pipe driver to flush now if already on validate list,
* Otherwise we'll overwrite previous contents.
*/
if (!(flags & PIPE_MAP_UNSYNCHRONIZED) &&
if (!(flags & PIPE_MAP_UNSYNCHRONIZED) &&
p_atomic_read(&vsrf->validated)) {
*retry = true;
goto out_unlock;
@@ -240,7 +240,7 @@ vmw_svga_winsys_surface_reference(struct vmw_svga_winsys_surface **pdst,
struct pipe_reference *dst_ref;
struct vmw_svga_winsys_surface *dst;
if(pdst == NULL || *pdst == src)
if (pdst == NULL || *pdst == src)
return;
dst = *pdst;
src/gallium/winsys/svga/drm/vmw_surface.h
+1 -1
View File
@@ -8,7 +8,7 @@
/**
* @file
* Surfaces for VMware SVGA winsys.
*
*
* @author Jose Fonseca <jfonseca@vmware.com>
*/