gallium/radeon: use TCC line size as alignment in other places

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2017-02-15 18:49:11 +01:00
parent 791e8ce04a
commit a550fbb510
4 changed files with 9 additions and 5 deletions
@@ -369,7 +369,8 @@ static void *r600_buffer_transfer_map(struct pipe_context *ctx,
u_upload_alloc(ctx->stream_uploader, 0,
box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
256, &offset, (struct pipe_resource**)&staging,
rctx->screen->info.tcc_cache_line_size,
&offset, (struct pipe_resource**)&staging,
(void**)&data);
if (staging) {
@@ -193,7 +193,8 @@ void r600_draw_rectangle(struct blitter_context *blitter,
/* Upload vertices. The hw rectangle has only 3 vertices,
* I guess the 4th one is derived from the first 3.
* The vertex specification should match u_blitter's vertex element state. */
u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24, 256,
u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
rctx->screen->info.tcc_cache_line_size,
&offset, &buf, (void**)&vb);
if (!buf)
return;
+2 -1
View File
@@ -565,7 +565,8 @@ static void si_upload_compute_input(struct si_context *sctx,
/* The extra num_work_size_bytes are for work group / work item size information */
kernel_args_size = program->input_size + num_work_size_bytes;
u_upload_alloc(sctx->b.b.stream_uploader, 0, kernel_args_size, 256,
u_upload_alloc(sctx->b.b.stream_uploader, 0, kernel_args_size,
sctx->screen->b.info.tcc_cache_line_size,
&kernel_args_offset,
(struct pipe_resource**)&input_buffer, &kernel_args_ptr);
@@ -137,8 +137,9 @@ static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned s
unsigned *out_offset, struct r600_resource **out_buf) {
uint64_t va;
u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
(struct pipe_resource**)out_buf);
u_suballocator_alloc(sctx->ce_suballocator, size,
sctx->screen->b.info.tcc_cache_line_size,
out_offset, (struct pipe_resource**)out_buf);
if (!out_buf)
return false;