r600: avoid setting invalid bit on r7xx for blits

2010-04-26 13:45:01 -04:00
parent 06574e45b4
commit a53e8b7def
1 changed files with 4 additions and 0 deletions
@@ -344,6 +344,10 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
            return;
    }

+    /* must be 0 on r7xx */
+    if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
+	    CLEARbit(cb_color0_info, BLEND_FLOAT32_bit);
+
    SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
             CB_COLOR0_INFO__FORMAT_mask);
    SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);