nak: Simplify I/O gathering
This adds mark_attrs_(read|written)() helpers to VtgIoInfo which take a range of attribute addresses and mark the range as-needed. It adds a similar mark_attr_read() helper to FragmentIoInfo which only marks a single address and takes a PixelImap. This gets us down to only needing to duplicate the address range if ladder twice. For VTG I/O, having it take ranges will be more ergonamic when it comes time to handle non- constant I/O offsets. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
This commit is contained in:
Faith Ekstrand
committed by
Marge Bot
Marge Bot
parent
32910d3016
commit
a4ff5a9fc6
@@ -1370,28 +1370,13 @@ impl<'a> ShaderFromNir<'a> {
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+ u16::try_from(intrin.component()).unwrap() * 4;
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for c in 0..comps {
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let attribute_id = addr + 4 * u16::from(c);
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let c_addr = addr + 4 * u16::from(c);
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if attribute_id < 0x080 {
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io.sysvals_in.ab |= 1 << (attribute_id / 4);
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} else if attribute_id >= 0x080
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&& attribute_id < 0x280
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{
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let user_attribute_index =
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(attribute_id - 0x080) as usize / 4;
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io.attr_in[user_attribute_index] =
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PixelImap::Constant;
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} else if attribute_id >= 0x2c0
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&& attribute_id < 0x300
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{
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io.sysvals_in.c |=
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1 << ((attribute_id - 0x2c0) / 4);
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}
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io.mark_attr_read(c_addr, PixelImap::Constant);
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b.push_op(OpIpa {
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dst: dst[usize::from(c)].into(),
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addr: attribute_id,
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addr: c_addr,
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freq: InterpFreq::Constant,
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loc: InterpLoc::Default,
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offset: SrcRef::Zero.into(),
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@@ -1402,6 +1387,9 @@ impl<'a> ShaderFromNir<'a> {
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let addr = u16::try_from(intrin.base()).unwrap()
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+ u16::try_from(intrin.component()).unwrap() * 4;
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let addr_range = addr..(addr + 4 * u16::from(comps));
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io.mark_attrs_read(addr_range);
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let access = AttrAccess {
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addr: addr,
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comps: comps,
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@@ -1410,29 +1398,6 @@ impl<'a> ShaderFromNir<'a> {
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flags: 0,
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};
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let attribute_base_index = access.addr / 4;
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for attribute_index in attribute_base_index
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..attribute_base_index + access.comps as u16
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{
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let attribute_id = attribute_index * 4;
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if attribute_id < 0x080 {
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io.sysvals_in.ab |= 1 << (attribute_id / 4);
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} else if attribute_id >= 0x080
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&& attribute_id < 0x280
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{
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BitMutView::new(&mut io.attr_in).set_bit(
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(attribute_id as usize - 0x080) / 4,
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true,
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);
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} else if attribute_id >= 0x2c0
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&& attribute_id < 0x300
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{
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io.sysvals_in.c |=
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1 << ((attribute_id - 0x2c0) / 4);
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}
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}
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b.push_op(OpALd {
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dst: dst.into(),
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vtx: vtx,
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@@ -1487,65 +1452,21 @@ impl<'a> ShaderFromNir<'a> {
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};
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assert!(intrin.def.bit_size() == 32);
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let dst =
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b.alloc_ssa(RegFile::GPR, intrin.def.num_components());
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let comps = intrin.def.num_components();
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let dst = b.alloc_ssa(RegFile::GPR, comps);
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for c in 0..intrin.def.num_components() {
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let attribute_id = addr + 4 * u16::from(c);
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let ShaderIoInfo::Fragment(io) = &mut self.info.io else {
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panic!("input interpolation is only allowed in fragment shaders");
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};
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if attribute_id < 0x080 {
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match &mut self.info.io {
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ShaderIoInfo::None => {
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panic!("Stage does not support load_interpolated_input")
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}
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ShaderIoInfo::Vtg(VtgIoInfo {
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sysvals_in, ..
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})
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| ShaderIoInfo::Fragment(FragmentIoInfo {
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sysvals_in,
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..
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}) => {
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sysvals_in.ab |= 1 << (attribute_id / 4);
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}
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}
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} else if attribute_id >= 0x080 && attribute_id < 0x280 {
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let user_attribute_index =
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(attribute_id - 0x080) as usize / 4;
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for c in 0..comps {
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let c_addr = addr + 4 * u16::from(c);
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match &mut self.info.io {
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ShaderIoInfo::None => {
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panic!("Stage does not support load_interpolated_input")
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}
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ShaderIoInfo::Vtg(io) => {
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BitMutView::new(&mut io.attr_in)
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.set_bit(user_attribute_index, true);
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}
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ShaderIoInfo::Fragment(io) => {
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io.attr_in[user_attribute_index] = interp_mode;
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}
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_ => {}
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}
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} else if attribute_id >= 0x2c0 && attribute_id < 0x300 {
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match &mut self.info.io {
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ShaderIoInfo::None => {
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panic!("Stage does not support load_interpolated_input")
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}
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ShaderIoInfo::Vtg(VtgIoInfo {
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sysvals_in, ..
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})
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| ShaderIoInfo::Fragment(FragmentIoInfo {
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sysvals_in,
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..
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}) => {
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sysvals_in.c |=
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1 << ((attribute_id - 0x2c0) / 4);
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}
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}
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}
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io.mark_attr_read(c_addr, interp_mode);
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b.push_op(OpIpa {
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dst: dst[usize::from(c)].into(),
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addr: attribute_id,
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addr: c_addr,
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freq: freq,
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loc: loc,
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offset: offset,
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@@ -1757,6 +1678,9 @@ impl<'a> ShaderFromNir<'a> {
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});
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}
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nir_intrinsic_store_output => {
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assert!(intrin.get_src(0).bit_size() == 32);
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let comps = intrin.num_components;
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let data = self.get_src(&srcs[0]);
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let vtx = Src::new_zero();
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let offset = self.get_src(&srcs[1]);
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@@ -1773,7 +1697,7 @@ impl<'a> ShaderFromNir<'a> {
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assert!(srcs[1].is_zero());
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let base: usize = intrin.base().try_into().unwrap();
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assert!(base % 4 == 0);
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for c in 0..usize::from(intrin.num_components) {
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for c in 0..usize::from(comps) {
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self.fs_out_regs[(base / 4) + c] = data[c];
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}
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}
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@@ -1781,38 +1705,17 @@ impl<'a> ShaderFromNir<'a> {
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let addr = u16::try_from(intrin.base()).unwrap()
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+ u16::try_from(intrin.component()).unwrap() * 4;
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assert!(intrin.get_src(0).bit_size() == 32);
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let addr_range = addr..(addr + 4 * u16::from(comps));
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io.mark_attrs_written(addr_range);
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let access = AttrAccess {
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addr: addr,
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comps: intrin.get_src(0).num_components(),
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comps: comps,
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patch: false,
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out_load: false,
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flags: 0,
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};
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let attribute_base_index = access.addr / 4;
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for attribute_index in attribute_base_index
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..attribute_base_index + access.comps as u16
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{
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let attribute_id = attribute_index * 4;
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if attribute_id < 0x080 {
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io.sysvals_out.ab |= 1 << (attribute_id / 4);
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} else if attribute_id >= 0x080
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&& attribute_id < 0x280
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{
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BitMutView::new(&mut io.attr_out).set_bit(
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(attribute_id as usize - 0x080) / 4,
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true,
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);
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} else if attribute_id >= 0x2c0
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&& attribute_id < 0x300
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{
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io.sysvals_out.c |=
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1 << ((attribute_id - 0x2c0) / 4);
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}
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}
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b.push_op(OpASt {
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vtx: vtx,
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offset: offset,
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@@ -4529,6 +4529,45 @@ pub struct VtgIoInfo {
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pub store_req_end: u8,
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}
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impl VtgIoInfo {
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fn mark_attrs(&mut self, addrs: Range<u16>, written: bool) {
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let sysvals = if written {
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&mut self.sysvals_out
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} else {
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&mut self.sysvals_in
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};
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let mut attr = BitMutView::new(if written {
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&mut self.attr_out
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} else {
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&mut self.attr_in
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});
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let mut addrs = addrs;
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addrs.start &= !3;
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for addr in addrs.step_by(4) {
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if addr < 0x080 {
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sysvals.ab |= 1 << (addr / 4);
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} else if addr < 0x280 {
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let attr_idx = (addr - 0x080) as usize / 4;
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attr.set_bit(attr_idx, true);
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} else if addr < 0x2c0 {
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panic!("FF color I/O not supported");
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} else if addr < 0x300 {
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sysvals.c |= 1 << ((addr - 0x2c0) / 4);
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}
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}
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}
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pub fn mark_attrs_read(&mut self, addrs: Range<u16>) {
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self.mark_attrs(addrs, false);
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}
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pub fn mark_attrs_written(&mut self, addrs: Range<u16>) {
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self.mark_attrs(addrs, true);
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}
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}
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#[derive(Debug)]
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pub struct FragmentIoInfo {
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pub sysvals_in: SysValInfo,
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@@ -4541,6 +4580,21 @@ pub struct FragmentIoInfo {
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pub writes_depth: bool,
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}
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impl FragmentIoInfo {
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pub fn mark_attr_read(&mut self, addr: u16, interp: PixelImap) {
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if addr < 0x080 {
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self.sysvals_in.ab |= 1 << (addr / 4);
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} else if addr < 0x280 {
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let attr_idx = (addr - 0x080) as usize / 4;
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self.attr_in[attr_idx] = interp;
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} else if addr < 0x2c0 {
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panic!("FF color I/O not supported");
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} else if addr < 0x300 {
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self.sysvals_in.c |= 1 << ((addr - 0x2c0) / 4);
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}
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}
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}
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#[derive(Debug)]
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pub enum ShaderIoInfo {
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None,
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