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r600g: don't use register mask for PA_CL_CLIP_CNTL

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Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák
2012-01-29 07:16:10 +01:00
parent 97acf2ca59
commit a494301f7f
4 changed files with 19 additions and 22 deletions
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src/gallium/drivers/r600/evergreen_state.c
+5 -5
View File
@@ -909,6 +909,11 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
S_028814_POLY_MODE(polygon_dual_mode) |
S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
rs->pa_cl_clip_cntl =
S_028810_PS_UCP_MODE(3) |
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
@@ -980,11 +985,6 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
}
r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
S_028810_PS_UCP_MODE(3) | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1),
0xFFFFFFFF, NULL, 0);
return rstate;
}
src/gallium/drivers/r600/r600_pipe.h
+2 -1
View File
@@ -111,6 +111,7 @@ struct r600_pipe_rasterizer {
unsigned clip_plane_enable;
unsigned pa_sc_line_stipple;
unsigned pa_su_sc_mode_cntl;
unsigned pa_cl_clip_cntl;
float offset_units;
float offset_scale;
};
@@ -214,6 +215,7 @@ struct r600_pipe_context {
unsigned cb_color_control;
unsigned pa_sc_line_stipple;
unsigned pa_su_sc_mode_cntl;
unsigned pa_cl_clip_cntl;
/* for saving when using blitter */
struct pipe_stencil_ref stencil_ref;
struct pipe_viewport_state viewport;
@@ -234,7 +236,6 @@ struct r600_pipe_context {
unsigned saved_render_cond_mode;
/* shader information */
boolean two_side;
unsigned user_clip_plane_enable;
unsigned sprite_coord_enable;
boolean export_16bpc;
unsigned alpha_ref;
src/gallium/drivers/r600/r600_state.c
+5 -5
View File
@@ -963,6 +963,11 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
S_028814_POLY_MODE(polygon_dual_mode) |
S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
rs->pa_cl_clip_cntl =
S_028810_PS_UCP_MODE(3) |
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
/* offset */
@@ -1026,11 +1031,6 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
S_028810_PS_UCP_MODE(3) | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1),
0xFFFFFFFF, NULL, 0);
return rstate;
}
src/gallium/drivers/r600/r600_state_common.c
+7 -11
View File
@@ -168,6 +168,7 @@ void r600_bind_rs_state(struct pipe_context *ctx, void *state)
rctx->two_side = rs->two_side;
rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
rctx->rasterizer = rs;
@@ -622,20 +623,9 @@ static void r600_update_derived_state(struct r600_pipe_context *rctx)
{
struct pipe_context * ctx = (struct pipe_context*)rctx;
struct r600_pipe_state rstate;
unsigned user_clip_plane_enable;
if (rctx->vs_shader->shader.clip_dist_write || rctx->vs_shader->shader.vs_prohibit_ucps)
user_clip_plane_enable = 0;
else
user_clip_plane_enable = rctx->rasterizer->clip_plane_enable & 0x3F;
rstate.nregs = 0;
if (user_clip_plane_enable != rctx->user_clip_plane_enable) {
r600_pipe_state_add_reg(&rstate, R_028810_PA_CL_CLIP_CNTL, user_clip_plane_enable , 0x3F, NULL, 0);
rctx->user_clip_plane_enable = user_clip_plane_enable;
}
if (rstate.nregs)
r600_context_pipe_state_set(&rctx->ctx, &rstate);
@@ -752,6 +742,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
if (rctx->chip_class <= R700)
r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, 0xFFFFFFFF, NULL, 0);
}
rctx->vgt.nregs = 0;
@@ -781,6 +772,11 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
r600_pipe_state_mod_reg(&rctx->vgt,
rctx->vs_shader->pa_cl_vs_out_cntl |
(rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
r600_pipe_state_mod_reg(&rctx->vgt,
rctx->pa_cl_clip_cntl |
(rctx->vs_shader->shader.clip_dist_write ||
rctx->vs_shader->shader.vs_prohibit_ucps ?
0 : rctx->rasterizer->clip_plane_enable & 0x3F));
r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);