radeonsi: always use SDMA for big buffer clears and first buffer uses
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
@@ -168,6 +168,7 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
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enum r600_coherency coher)
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{
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struct si_context *sctx = (struct si_context*)ctx;
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struct radeon_winsys *ws = sctx->b.ws;
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unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher);
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unsigned flush_flags = get_flush_flags(sctx, coher);
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@@ -193,6 +194,25 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
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return;
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}
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/* dma_clear_buffer can use clear_buffer on failure. Make sure that
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* doesn't happen. We don't want an infinite recursion: */
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if (sctx->b.chip_class >= CIK && sctx->b.dma.cs &&
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/* CP DMA is very slow. Always use SDMA for big clears. This
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* alone improves DeusEx:MD performance by 70%. */
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(size > 128 * 1024 ||
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/* Buffers not used by the GFX IB yet will be cleared by SDMA.
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* This happens to move most buffer clears to SDMA, including
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* DCC and CMASK clears, because pipe->clear clears them before
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* si_emit_framebuffer_state (in a draw call) adds them.
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* For example, DeusEx:MD has 21 buffer clears per frame and all
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* of them are moved to SDMA thanks to this. */
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!ws->cs_is_buffer_referenced(sctx->b.gfx.cs,
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r600_resource(dst)->buf,
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RADEON_USAGE_READWRITE))) {
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sctx->b.dma_clear_buffer(ctx, dst, offset, size, value);
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return;
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}
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uint64_t va = r600_resource(dst)->gpu_address + offset;
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/* Flush the caches. */
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