tgsi/scan: move src operand processing into a separate function
the next commit will need this Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
@@ -102,6 +102,186 @@ computes_derivative(unsigned opcode)
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}
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static void
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scan_src_operand(struct tgsi_shader_info *info,
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const struct tgsi_full_instruction *fullinst,
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const struct tgsi_full_src_register *src,
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unsigned src_index,
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unsigned usage_mask,
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bool is_interp_instruction,
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bool *is_mem_inst)
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{
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int ind = src->Register.Index;
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/* Mark which inputs are effectively used */
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if (src->Register.File == TGSI_FILE_INPUT) {
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if (src->Register.Indirect) {
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for (ind = 0; ind < info->num_inputs; ++ind) {
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info->input_usage_mask[ind] |= usage_mask;
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}
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} else {
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assert(ind >= 0);
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assert(ind < PIPE_MAX_SHADER_INPUTS);
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info->input_usage_mask[ind] |= usage_mask;
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}
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if (info->processor == PIPE_SHADER_FRAGMENT) {
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unsigned name, index, input;
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if (src->Register.Indirect && src->Indirect.ArrayID)
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input = info->input_array_first[src->Indirect.ArrayID];
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else
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input = src->Register.Index;
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name = info->input_semantic_name[input];
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index = info->input_semantic_index[input];
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if (name == TGSI_SEMANTIC_POSITION &&
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(src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
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src->Register.SwizzleY == TGSI_SWIZZLE_Z ||
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src->Register.SwizzleZ == TGSI_SWIZZLE_Z ||
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src->Register.SwizzleW == TGSI_SWIZZLE_Z))
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info->reads_z = TRUE;
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if (name == TGSI_SEMANTIC_COLOR) {
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unsigned mask =
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(1 << src->Register.SwizzleX) |
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(1 << src->Register.SwizzleY) |
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(1 << src->Register.SwizzleZ) |
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(1 << src->Register.SwizzleW);
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info->colors_read |= mask << (index * 4);
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}
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/* Process only interpolated varyings. Don't include POSITION.
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* Don't include integer varyings, because they are not
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* interpolated. Don't process inputs interpolated by INTERP
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* opcodes. Those are tracked separately.
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*/
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if ((!is_interp_instruction || src_index != 0) &&
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(name == TGSI_SEMANTIC_GENERIC ||
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name == TGSI_SEMANTIC_TEXCOORD ||
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name == TGSI_SEMANTIC_COLOR ||
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name == TGSI_SEMANTIC_BCOLOR ||
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name == TGSI_SEMANTIC_FOG ||
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name == TGSI_SEMANTIC_CLIPDIST)) {
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switch (info->input_interpolate[input]) {
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case TGSI_INTERPOLATE_COLOR:
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case TGSI_INTERPOLATE_PERSPECTIVE:
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switch (info->input_interpolate_loc[input]) {
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case TGSI_INTERPOLATE_LOC_CENTER:
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info->uses_persp_center = TRUE;
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break;
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case TGSI_INTERPOLATE_LOC_CENTROID:
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info->uses_persp_centroid = TRUE;
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break;
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case TGSI_INTERPOLATE_LOC_SAMPLE:
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info->uses_persp_sample = TRUE;
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break;
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}
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break;
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case TGSI_INTERPOLATE_LINEAR:
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switch (info->input_interpolate_loc[input]) {
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case TGSI_INTERPOLATE_LOC_CENTER:
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info->uses_linear_center = TRUE;
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break;
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case TGSI_INTERPOLATE_LOC_CENTROID:
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info->uses_linear_centroid = TRUE;
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break;
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case TGSI_INTERPOLATE_LOC_SAMPLE:
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info->uses_linear_sample = TRUE;
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break;
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}
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break;
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/* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
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}
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}
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}
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}
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/* check for indirect register reads */
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if (src->Register.Indirect) {
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info->indirect_files |= (1 << src->Register.File);
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info->indirect_files_read |= (1 << src->Register.File);
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/* record indirect constant buffer indexing */
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if (src->Register.File == TGSI_FILE_CONSTANT) {
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if (src->Register.Dimension) {
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if (src->Dimension.Indirect)
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info->const_buffers_indirect = info->const_buffers_declared;
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else
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info->const_buffers_indirect |= 1u << src->Dimension.Index;
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} else {
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info->const_buffers_indirect |= 1;
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}
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}
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}
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if (src->Register.Dimension && src->Dimension.Indirect)
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info->dim_indirect_files |= 1u << src->Register.File;
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/* Texture samplers */
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if (src->Register.File == TGSI_FILE_SAMPLER) {
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const unsigned index = src->Register.Index;
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assert(fullinst->Instruction.Texture);
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assert(index < ARRAY_SIZE(info->is_msaa_sampler));
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assert(index < PIPE_MAX_SAMPLERS);
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if (is_texture_inst(fullinst->Instruction.Opcode)) {
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const unsigned target = fullinst->Texture.Texture;
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assert(target < TGSI_TEXTURE_UNKNOWN);
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/* for texture instructions, check that the texture instruction
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* target matches the previous sampler view declaration (if there
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* was one.)
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*/
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if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
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/* probably no sampler view declaration */
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info->sampler_targets[index] = target;
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} else {
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/* Make sure the texture instruction's sampler/target info
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* agrees with the sampler view declaration.
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*/
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assert(info->sampler_targets[index] == target);
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}
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/* MSAA samplers */
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if (target == TGSI_TEXTURE_2D_MSAA ||
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target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
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info->is_msaa_sampler[src->Register.Index] = TRUE;
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}
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}
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}
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if (is_memory_file(src->Register.File) &&
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!is_mem_query_inst(fullinst->Instruction.Opcode)) {
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*is_mem_inst = true;
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if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
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info->writes_memory = TRUE;
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if (src->Register.File == TGSI_FILE_IMAGE) {
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if (src->Register.Indirect)
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info->images_writemask = info->images_declared;
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else
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info->images_writemask |= 1 << src->Register.Index;
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} else if (src->Register.File == TGSI_FILE_BUFFER) {
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if (src->Register.Indirect)
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info->shader_buffers_atomic = info->shader_buffers_declared;
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else
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info->shader_buffers_atomic |= 1 << src->Register.Index;
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}
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} else {
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if (src->Register.File == TGSI_FILE_BUFFER) {
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if (src->Register.Indirect)
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info->shader_buffers_load = info->shader_buffers_declared;
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else
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info->shader_buffers_load |= 1 << src->Register.Index;
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}
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}
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}
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}
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static void
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scan_instruction(struct tgsi_shader_info *info,
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const struct tgsi_full_instruction *fullinst,
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@@ -183,177 +363,9 @@ scan_instruction(struct tgsi_shader_info *info,
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info->uses_doubles = TRUE;
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for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
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const struct tgsi_full_src_register *src = &fullinst->Src[i];
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int ind = src->Register.Index;
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/* Mark which inputs are effectively used */
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if (src->Register.File == TGSI_FILE_INPUT) {
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unsigned usage_mask;
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usage_mask = tgsi_util_get_inst_usage_mask(fullinst, i);
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if (src->Register.Indirect) {
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for (ind = 0; ind < info->num_inputs; ++ind) {
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info->input_usage_mask[ind] |= usage_mask;
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}
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} else {
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assert(ind >= 0);
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assert(ind < PIPE_MAX_SHADER_INPUTS);
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info->input_usage_mask[ind] |= usage_mask;
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}
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if (info->processor == PIPE_SHADER_FRAGMENT) {
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unsigned name, index, input;
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if (src->Register.Indirect && src->Indirect.ArrayID)
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input = info->input_array_first[src->Indirect.ArrayID];
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else
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input = src->Register.Index;
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name = info->input_semantic_name[input];
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index = info->input_semantic_index[input];
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if (name == TGSI_SEMANTIC_POSITION &&
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(src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
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src->Register.SwizzleY == TGSI_SWIZZLE_Z ||
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src->Register.SwizzleZ == TGSI_SWIZZLE_Z ||
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src->Register.SwizzleW == TGSI_SWIZZLE_Z))
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info->reads_z = TRUE;
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if (name == TGSI_SEMANTIC_COLOR) {
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unsigned mask =
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(1 << src->Register.SwizzleX) |
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(1 << src->Register.SwizzleY) |
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(1 << src->Register.SwizzleZ) |
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(1 << src->Register.SwizzleW);
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info->colors_read |= mask << (index * 4);
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}
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/* Process only interpolated varyings. Don't include POSITION.
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* Don't include integer varyings, because they are not
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* interpolated. Don't process inputs interpolated by INTERP
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* opcodes. Those are tracked separately.
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*/
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if ((!is_interp_instruction || i != 0) &&
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(name == TGSI_SEMANTIC_GENERIC ||
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name == TGSI_SEMANTIC_TEXCOORD ||
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name == TGSI_SEMANTIC_COLOR ||
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name == TGSI_SEMANTIC_BCOLOR ||
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name == TGSI_SEMANTIC_FOG ||
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name == TGSI_SEMANTIC_CLIPDIST)) {
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switch (info->input_interpolate[input]) {
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case TGSI_INTERPOLATE_COLOR:
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case TGSI_INTERPOLATE_PERSPECTIVE:
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switch (info->input_interpolate_loc[input]) {
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case TGSI_INTERPOLATE_LOC_CENTER:
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info->uses_persp_center = TRUE;
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break;
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case TGSI_INTERPOLATE_LOC_CENTROID:
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info->uses_persp_centroid = TRUE;
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break;
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case TGSI_INTERPOLATE_LOC_SAMPLE:
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info->uses_persp_sample = TRUE;
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break;
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}
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break;
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case TGSI_INTERPOLATE_LINEAR:
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switch (info->input_interpolate_loc[input]) {
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case TGSI_INTERPOLATE_LOC_CENTER:
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info->uses_linear_center = TRUE;
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break;
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case TGSI_INTERPOLATE_LOC_CENTROID:
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info->uses_linear_centroid = TRUE;
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break;
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case TGSI_INTERPOLATE_LOC_SAMPLE:
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info->uses_linear_sample = TRUE;
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break;
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}
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break;
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/* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
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}
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}
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}
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}
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/* check for indirect register reads */
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if (src->Register.Indirect) {
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info->indirect_files |= (1 << src->Register.File);
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info->indirect_files_read |= (1 << src->Register.File);
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/* record indirect constant buffer indexing */
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if (src->Register.File == TGSI_FILE_CONSTANT) {
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if (src->Register.Dimension) {
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if (src->Dimension.Indirect)
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info->const_buffers_indirect = info->const_buffers_declared;
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else
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info->const_buffers_indirect |= 1u << src->Dimension.Index;
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} else {
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info->const_buffers_indirect |= 1;
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}
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}
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}
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if (src->Register.Dimension && src->Dimension.Indirect)
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info->dim_indirect_files |= 1u << src->Register.File;
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/* Texture samplers */
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if (src->Register.File == TGSI_FILE_SAMPLER) {
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const unsigned index = src->Register.Index;
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assert(fullinst->Instruction.Texture);
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assert(index < ARRAY_SIZE(info->is_msaa_sampler));
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assert(index < PIPE_MAX_SAMPLERS);
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if (is_texture_inst(fullinst->Instruction.Opcode)) {
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const unsigned target = fullinst->Texture.Texture;
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assert(target < TGSI_TEXTURE_UNKNOWN);
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/* for texture instructions, check that the texture instruction
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* target matches the previous sampler view declaration (if there
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* was one.)
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*/
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if (info->sampler_targets[index] == TGSI_TEXTURE_UNKNOWN) {
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/* probably no sampler view declaration */
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info->sampler_targets[index] = target;
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} else {
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/* Make sure the texture instruction's sampler/target info
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* agrees with the sampler view declaration.
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*/
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assert(info->sampler_targets[index] == target);
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}
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/* MSAA samplers */
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if (target == TGSI_TEXTURE_2D_MSAA ||
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target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
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info->is_msaa_sampler[src->Register.Index] = TRUE;
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}
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}
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}
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if (is_memory_file(src->Register.File) &&
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!is_mem_query_inst(fullinst->Instruction.Opcode)) {
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is_mem_inst = true;
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if (tgsi_get_opcode_info(fullinst->Instruction.Opcode)->is_store) {
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info->writes_memory = TRUE;
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if (src->Register.File == TGSI_FILE_IMAGE) {
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if (src->Register.Indirect)
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info->images_writemask = info->images_declared;
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else
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info->images_writemask |= 1 << src->Register.Index;
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} else if (src->Register.File == TGSI_FILE_BUFFER) {
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if (src->Register.Indirect)
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info->shader_buffers_atomic = info->shader_buffers_declared;
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else
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info->shader_buffers_atomic |= 1 << src->Register.Index;
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}
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} else {
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if (src->Register.File == TGSI_FILE_BUFFER) {
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if (src->Register.Indirect)
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info->shader_buffers_load = info->shader_buffers_declared;
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else
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info->shader_buffers_load |= 1 << src->Register.Index;
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}
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}
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}
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scan_src_operand(info, fullinst, &fullinst->Src[i], i,
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tgsi_util_get_inst_usage_mask(fullinst, i),
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is_interp_instruction, &is_mem_inst);
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}
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/* check for indirect register writes */
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