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i965/hsw: Change L3 MOCS of 3DSTATE_VERTEX_BUFFERS

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Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
This commit is contained in:
Chad Versace
2013-07-18 09:58:06 -07:00
parent eb83079b35
commit a16d47465e
2 changed files with 6 additions and 0 deletions
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3
src/mesa/drivers/dri/i965/brw_draw_upload.c
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@@ -658,6 +658,9 @@ static void brw_emit_vertices(struct brw_context *brw)
if (brw->gen >= 7)
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
if (brw->is_haswell)
dw0 |= GEN7_MOCS_L3 << 16;
OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT));
OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
if (brw->gen >= 5) {

3
src/mesa/drivers/dri/i965/gen6_blorp.cpp
View File

@@ -163,6 +163,9 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
if (brw->gen >= 7)
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
if (brw->is_haswell)
dw0 |= GEN7_MOCS_L3 << 16;
BEGIN_BATCH(batch_length);
OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
OUT_BATCH(dw0);