r600g: DP4 also supports writemasking
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@@ -1668,15 +1668,13 @@ static int tgsi_dp(struct r600_shader_ctx *ctx)
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alu.src[j] = r600_src[j];
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alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
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}
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if(inst->Dst[0].Register.WriteMask & (1 << i)) {
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r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
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if (r)
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return r;
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} else {
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alu.dst.sel = ctx->temp_reg;
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}
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r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
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if (r)
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return r;
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alu.dst.chan = i;
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alu.dst.write = 1;
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alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
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/* handle some special cases */
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switch (ctx->inst_info->tgsi_opcode) {
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case TGSI_OPCODE_DP2:
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