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broadcom/qpu: clean all versions not supported

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Right now we only support V3D 4.2 and V3D 7.1, so clean older versions
that were left in the QPU.

Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30000>
This commit is contained in:
Juan A. Suarez Romero
2024-07-02 13:25:46 +02:00
committed by Marge Bot
parent aa4d0836fe
commit a10957adb6
3 changed files with 84 additions and 156 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/broadcom/qpu/qpu_disasm.c
+4 -4
View File
@@ -56,7 +56,7 @@ pad_to(struct disasm_state *disasm, int n)
static void
v3d33_qpu_disasm_raddr(struct disasm_state *disasm,
v3d42_qpu_disasm_raddr(struct disasm_state *disasm,
const struct v3d_qpu_instr *instr,
enum v3d_qpu_mux mux)
{
@@ -135,10 +135,10 @@ v3d_qpu_disasm_raddr(struct disasm_state *disasm,
const struct v3d_qpu_input *input,
enum v3d_qpu_input_class input_class)
{
if (disasm->devinfo->ver < 71)
v3d33_qpu_disasm_raddr(disasm, instr, input->mux);
else
if (disasm->devinfo->ver >= 71)
v3d71_qpu_disasm_raddr(disasm, instr, input->raddr, input_class);
else
v3d42_qpu_disasm_raddr(disasm, instr, input->mux);
}
static void
src/broadcom/qpu/qpu_pack.c
+32 -102
View File
@@ -128,69 +128,7 @@
#define SMIMM_C .small_imm_c = true
#define SMIMM_D .small_imm_d = true
static const struct v3d_qpu_sig v33_sig_map[] = {
/* MISC R3 R4 R5 */
[0] = { },
[1] = { THRSW, },
[2] = { LDUNIF },
[3] = { THRSW, LDUNIF },
[4] = { LDTMU, },
[5] = { THRSW, LDTMU, },
[6] = { LDTMU, LDUNIF },
[7] = { THRSW, LDTMU, LDUNIF },
[8] = { LDVARY, },
[9] = { THRSW, LDVARY, },
[10] = { LDVARY, LDUNIF },
[11] = { THRSW, LDVARY, LDUNIF },
[12] = { LDVARY, LDTMU, },
[13] = { THRSW, LDVARY, LDTMU, },
[14] = { SMIMM_B, LDVARY, },
[15] = { SMIMM_B, },
[16] = { LDTLB, },
[17] = { LDTLBU, },
/* 18-21 reserved */
[22] = { UCB, },
[23] = { ROT, },
[24] = { LDVPM, },
[25] = { THRSW, LDVPM, },
[26] = { LDVPM, LDUNIF },
[27] = { THRSW, LDVPM, LDUNIF },
[28] = { LDVPM, LDTMU, },
[29] = { THRSW, LDVPM, LDTMU, },
[30] = { SMIMM_B, LDVPM, },
[31] = { SMIMM_B, },
};
static const struct v3d_qpu_sig v40_sig_map[] = {
/* MISC R3 R4 R5 */
[0] = { },
[1] = { THRSW, },
[2] = { LDUNIF },
[3] = { THRSW, LDUNIF },
[4] = { LDTMU, },
[5] = { THRSW, LDTMU, },
[6] = { LDTMU, LDUNIF },
[7] = { THRSW, LDTMU, LDUNIF },
[8] = { LDVARY, },
[9] = { THRSW, LDVARY, },
[10] = { LDVARY, LDUNIF },
[11] = { THRSW, LDVARY, LDUNIF },
/* 12-13 reserved */
[14] = { SMIMM_B, LDVARY, },
[15] = { SMIMM_B, },
[16] = { LDTLB, },
[17] = { LDTLBU, },
[18] = { WRTMUC },
[19] = { THRSW, WRTMUC },
[20] = { LDVARY, WRTMUC },
[21] = { THRSW, LDVARY, WRTMUC },
[22] = { UCB, },
[23] = { ROT, },
/* 24-30 reserved */
[31] = { SMIMM_B, LDTMU, },
};
static const struct v3d_qpu_sig v41_sig_map[] = {
static const struct v3d_qpu_sig v42_sig_map[] = {
/* MISC phys R5 */
[0] = { },
[1] = { THRSW, },
@@ -263,21 +201,17 @@ v3d_qpu_sig_unpack(const struct v3d_device_info *devinfo,
uint32_t packed_sig,
struct v3d_qpu_sig *sig)
{
if (packed_sig >= ARRAY_SIZE(v33_sig_map))
if (packed_sig >= ARRAY_SIZE(v42_sig_map))
return false;
if (devinfo->ver >= 71)
*sig = v71_sig_map[packed_sig];
else if (devinfo->ver >= 41)
*sig = v41_sig_map[packed_sig];
else if (devinfo->ver == 40)
*sig = v40_sig_map[packed_sig];
else
*sig = v33_sig_map[packed_sig];
*sig = v42_sig_map[packed_sig];
/* Signals with zeroed unpacked contents after element 0 are reserved. */
return (packed_sig == 0 ||
memcmp(sig, &v33_sig_map[0], sizeof(*sig)) != 0);
memcmp(sig, &v42_sig_map[0], sizeof(*sig)) != 0);
}
bool
@@ -289,14 +223,10 @@ v3d_qpu_sig_pack(const struct v3d_device_info *devinfo,
if (devinfo->ver >= 71)
map = v71_sig_map;
else if (devinfo->ver >= 41)
map = v41_sig_map;
else if (devinfo->ver == 40)
map = v40_sig_map;
else
map = v33_sig_map;
map = v42_sig_map;
for (int i = 0; i < ARRAY_SIZE(v33_sig_map); i++) {
for (int i = 0; i < ARRAY_SIZE(v42_sig_map); i++) {
if (memcmp(&map[i], sig, sizeof(*sig)) == 0) {
*packed_sig = i;
return true;
@@ -524,7 +454,7 @@ struct opcode_desc {
uint8_t last_ver;
};
static const struct opcode_desc add_ops_v33[] = {
static const struct opcode_desc add_ops_v42[] = {
/* FADD is FADDNF depending on the order of the mux_a/mux_b. */
{ 0, 47, .mux.b_mask = ANYMUX, .mux.a_mask = ANYMUX, V3D_QPU_A_FADD },
{ 0, 47, .mux.b_mask = ANYMUX, .mux.a_mask = ANYMUX, V3D_QPU_A_FADDNF },
@@ -628,7 +558,7 @@ static const struct opcode_desc add_ops_v33[] = {
{ 252, 252, .mux.b_mask = OP_RANGE(4, 6), .mux.a_mask = ANYMUX, V3D_QPU_A_UTOF },
};
static const struct opcode_desc mul_ops_v33[] = {
static const struct opcode_desc mul_ops_v42[] = {
{ 1, 1, .mux.b_mask = ANYMUX, .mux.a_mask = ANYMUX, V3D_QPU_M_ADD },
{ 2, 2, .mux.b_mask = ANYMUX, .mux.a_mask = ANYMUX, V3D_QPU_M_SUB },
{ 3, 3, .mux.b_mask = ANYMUX, .mux.a_mask = ANYMUX, V3D_QPU_M_UMUL24 },
@@ -1064,7 +994,7 @@ v3d_qpu_float32_pack_pack(enum v3d_qpu_output_pack pack,
}
static bool
v3d33_qpu_add_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
v3d42_qpu_add_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
struct v3d_qpu_instr *instr)
{
uint32_t op = QPU_GET_FIELD(packed_inst, V3D_QPU_OP_ADD);
@@ -1082,8 +1012,8 @@ v3d33_qpu_add_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst
map_op = (map_op - 253 + 245);
const struct opcode_desc *desc =
lookup_opcode_from_packed(devinfo, add_ops_v33,
ARRAY_SIZE(add_ops_v33),
lookup_opcode_from_packed(devinfo, add_ops_v42,
ARRAY_SIZE(add_ops_v42),
map_op, mux_a, mux_b, 0);
if (!desc)
@@ -1399,14 +1329,14 @@ static bool
v3d_qpu_add_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
struct v3d_qpu_instr *instr)
{
if (devinfo->ver < 71)
return v3d33_qpu_add_unpack(devinfo, packed_inst, instr);
else
if (devinfo->ver >= 71)
return v3d71_qpu_add_unpack(devinfo, packed_inst, instr);
else
return v3d42_qpu_add_unpack(devinfo, packed_inst, instr);
}
static bool
v3d33_qpu_mul_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
v3d42_qpu_mul_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
struct v3d_qpu_instr *instr)
{
uint32_t op = QPU_GET_FIELD(packed_inst, V3D_QPU_OP_MUL);
@@ -1416,8 +1346,8 @@ v3d33_qpu_mul_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst
{
const struct opcode_desc *desc =
lookup_opcode_from_packed(devinfo,
mul_ops_v33,
ARRAY_SIZE(mul_ops_v33),
mul_ops_v42,
ARRAY_SIZE(mul_ops_v42),
op, mux_a, mux_b, 0);
if (!desc)
return false;
@@ -1567,10 +1497,10 @@ static bool
v3d_qpu_mul_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
struct v3d_qpu_instr *instr)
{
if (devinfo->ver < 71)
return v3d33_qpu_mul_unpack(devinfo, packed_inst, instr);
else
if (devinfo->ver >= 71)
return v3d71_qpu_mul_unpack(devinfo, packed_inst, instr);
else
return v3d42_qpu_mul_unpack(devinfo, packed_inst, instr);
}
static const struct opcode_desc *
@@ -1594,7 +1524,7 @@ lookup_opcode_from_instr(const struct v3d_device_info *devinfo,
}
static bool
v3d33_qpu_add_pack(const struct v3d_device_info *devinfo,
v3d42_qpu_add_pack(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
{
uint32_t waddr = instr->alu.add.waddr;
@@ -1602,8 +1532,8 @@ v3d33_qpu_add_pack(const struct v3d_device_info *devinfo,
uint32_t mux_b = instr->alu.add.b.mux;
int nsrc = v3d_qpu_add_op_num_src(instr->alu.add.op);
const struct opcode_desc *desc =
lookup_opcode_from_instr(devinfo, add_ops_v33,
ARRAY_SIZE(add_ops_v33),
lookup_opcode_from_instr(devinfo, add_ops_v42,
ARRAY_SIZE(add_ops_v42),
instr->alu.add.op);
if (!desc)
@@ -2072,7 +2002,7 @@ v3d71_qpu_add_pack(const struct v3d_device_info *devinfo,
}
static bool
v3d33_qpu_mul_pack(const struct v3d_device_info *devinfo,
v3d42_qpu_mul_pack(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
{
uint32_t mux_a = instr->alu.mul.a.mux;
@@ -2080,8 +2010,8 @@ v3d33_qpu_mul_pack(const struct v3d_device_info *devinfo,
int nsrc = v3d_qpu_mul_op_num_src(instr->alu.mul.op);
const struct opcode_desc *desc =
lookup_opcode_from_instr(devinfo, mul_ops_v33,
ARRAY_SIZE(mul_ops_v33),
lookup_opcode_from_instr(devinfo, mul_ops_v42,
ARRAY_SIZE(mul_ops_v42),
instr->alu.mul.op);
if (!desc)
@@ -2313,20 +2243,20 @@ static bool
v3d_qpu_add_pack(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
{
if (devinfo->ver < 71)
return v3d33_qpu_add_pack(devinfo, instr, packed_instr);
else
if (devinfo->ver >= 71)
return v3d71_qpu_add_pack(devinfo, instr, packed_instr);
else
return v3d42_qpu_add_pack(devinfo, instr, packed_instr);
}
static bool
v3d_qpu_mul_pack(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
{
if (devinfo->ver < 71)
return v3d33_qpu_mul_pack(devinfo, instr, packed_instr);
else
if (devinfo->ver >= 71)
return v3d71_qpu_mul_pack(devinfo, instr, packed_instr);
else
return v3d42_qpu_mul_pack(devinfo, instr, packed_instr);
}
static bool
src/broadcom/qpu/tests/qpu_disasm.c
+48 -50
View File
@@ -34,69 +34,67 @@ static const struct {
uint64_t inst;
const char *expected;
} tests[] = {
{ 33, 0x3d003186bb800000ull, "nop ; nop ; ldvary" },
{ 33, 0x3c20318105829000ull, "fadd r1, r1, r5 ; nop ; thrsw" },
{ 33, 0x3c403186bb81d000ull, "vpmsetup -, r5 ; nop ; ldunif" },
{ 33, 0x3f003186bb800000ull, "nop ; nop ; ldvpm" },
{ 33, 0x3c002380b6edb000ull, "or rf0, r3, r3 ; mov vpm, r3" },
{ 33, 0x57403006bbb80000ull, "nop ; fmul r0, rf0, r5 ; ldvpm; ldunif" },
{ 33, 0x9c094adef634b000ull, "ffloor.ifb rf30.l, r3 ; fmul.pushz rf43.l, r5, r1.h" },
{ 33, 0xb0044c56ba326840ull, "flpop rf22, rf33 ; fmul.pushz rf49.l, r4.h, r1.abs" },
{ 42, 0x3d003186bb800000ull, "nop ; nop ; ldvary.rf0" },
{ 42, 0x3c20318105829000ull, "fadd r1, r1, r5 ; nop ; thrsw" },
{ 42, 0x3c403186bb81d000ull, "vpmsetup -, r5 ; nop ; ldunif" },
{ 42, 0x3c002380b6edb000ull, "or rf0, r3, r3 ; mov vpm, r3" },
{ 42, 0x9c094adef634b000ull, "ffloor.ifb rf30.l, r3 ; fmul.pushz rf43.l, r5, r1.h" },
{ 42, 0xb0044c56ba326840ull, "flpop rf22, rf33 ; fmul.pushz rf49.l, r4.h, r1.abs" },
/* vfmul input packing */
{ 33, 0x101e8b6e8aad4000ull, "fmax.nornn rf46, r4.l, r2.l ; vfmul.ifnb rf45, r3, r5" },
{ 33, 0x1857d3c219825000ull, "faddnf.norc r2.l, r5.l, r4 ; vfmul.ifb rf15, r0.ll, r4 ; ldunif" },
{ 33, 0x1c0a0dfde2294000ull, "fcmp.ifna rf61.h, r4.abs, r2.l; vfmul rf55, r2.hh, r1" },
{ 33, 0x2011c89b402cc000ull, "fsub.norz rf27, r4.abs, r1.abs; vfmul.ifa rf34, r3.swp, r1" },
{ 42, 0x101e8b6e8aad4000ull, "fmax.nornn rf46, r4.l, r2.l ; vfmul.ifnb rf45, r3, r5" },
{ 42, 0x1857d3c219825000ull, "faddnf.norc r2.l, r5.l, r4 ; vfmul.ifb rf15, r0.ll, r4 ; ldunif" },
{ 42, 0x1c0a0dfde2294000ull, "fcmp.ifna rf61.h, r4.abs, r2.l; vfmul rf55, r2.hh, r1" },
{ 42, 0x2011c89b402cc000ull, "fsub.norz rf27, r4.abs, r1.abs; vfmul.ifa rf34, r3.swp, r1" },
{ 33, 0xe01b42ab3bb063c0ull, "vfpack.andnc rf43, rf15.l, r0.h; fmul.ifna rf10.h, r4.l, r5.abs" },
{ 33, 0x600b8b87fb4d1000ull, "fdx.ifnb rf7.h, r1.l ; fmul.pushn rf46, r3.l, r2.abs" },
{ 42, 0xe01b42ab3bb063c0ull, "vfpack.andnc rf43, rf15.l, r0.h; fmul.ifna rf10.h, r4.l, r5.abs" },
{ 42, 0x600b8b87fb4d1000ull, "fdx.ifnb rf7.h, r1.l ; fmul.pushn rf46, r3.l, r2.abs" },
/* small immediates */
{ 33, 0x5de24398bbdc6218ull, "vflb.andnn rf24 ; fmul rf14, -8, rf8.h" },
{ 33, 0x25ef83d8b166f00full, "vfmin.pushn rf24, 15.ff, r5 ; smul24.ifnb rf15, r1, r3" },
{ 33, 0xadedcdf70839f990ull, "faddnf.pushc rf55, -16.l, r3.abs; fmul.ifb rf55.l, rf38.l, r1.h" },
{ 33, 0x7dff89fa6a01f020ull, "fsub.nornc rf58.h, 0x3b800000.l, r3.l; fmul.ifnb rf39, r0.h, r0.h" },
{ 42, 0x5de24398bbdc6218ull, "vflb.andnn rf24 ; fmul rf14, -8, rf8.h" },
{ 42, 0x25ef83d8b166f00full, "vfmin.pushn rf24, 15.ff, r5 ; smul24.ifnb rf15, r1, r3" },
{ 42, 0xadedcdf70839f990ull, "faddnf.pushc rf55, -16.l, r3.abs; fmul.ifb rf55.l, rf38.l, r1.h" },
{ 42, 0x7dff89fa6a01f020ull, "fsub.nornc rf58.h, 0x3b800000.l, r3.l; fmul.ifnb rf39, r0.h, r0.h" },
/* branch conditions */
{ 33, 0x02000006002034c0ull, "b.anyap rf19" },
{ 33, 0x02679356b4201000ull, "b.anyap -1268280496" },
{ 33, 0x02b76a2dd0400000ull, "b.anynaq zero_addr+0xd0b76a28" },
{ 33, 0x0200000500402000ull, "b.anynaq lri" },
{ 33, 0x0216fe167301c8c0ull, "bu.anya zero_addr+0x7316fe10, rf35" },
{ 33, 0x020000050040e000ull, "bu.anynaq lri, r:unif" },
{ 33, 0x0200000300006000ull, "bu.na0 lri, a:unif" },
{ 42, 0x02000006002034c0ull, "b.anyap rf19" },
{ 42, 0x02679356b4201000ull, "b.anyap -1268280496" },
{ 42, 0x02b76a2dd0400000ull, "b.anynaq zero_addr+0xd0b76a28" },
{ 42, 0x0200000500402000ull, "b.anynaq lri" },
{ 42, 0x0216fe167301c8c0ull, "bu.anya zero_addr+0x7316fe10, rf35" },
{ 42, 0x020000050040e000ull, "bu.anynaq lri, r:unif" },
{ 42, 0x0200000300006000ull, "bu.na0 lri, a:unif" },
/* Special waddr names */
{ 33, 0x3c00318735808000ull, "vfpack tlb, r0, r1 ; nop" },
{ 33, 0xe0571c938e8d5000ull, "fmax.andc recip, r5.h, r2.l ; fmul.ifb rf50.h, r3.l, r4.abs; ldunif" },
{ 33, 0xc04098d4382c9000ull, "add.pushn rsqrt, r1, r1 ; fmul rf35.h, r3.abs, r1.abs ; ldunif" },
{ 33, 0x481edcd6b3184500ull, "vfmin.norn log, r4.hh, r0 ; fmul.ifnb rf51, rf20.abs, r0.l" },
{ 33, 0x041618d57c453000ull, "shl.andn exp, r3, r2 ; add.ifb rf35, r1, r2" },
{ 33, 0x7048e5da49272800ull, "fsub.ifa rf26, r2.l, rf32 ; fmul.pushc sin, r1.h, r1.abs; ldunif" },
{ 42, 0x3c00318735808000ull, "vfpack tlb, r0, r1 ; nop" },
{ 42, 0xe0571c938e8d5000ull, "fmax.andc recip, r5.h, r2.l ; fmul.ifb rf50.h, r3.l, r4.abs; ldunif" },
{ 42, 0xc04098d4382c9000ull, "add.pushn rsqrt, r1, r1 ; fmul rf35.h, r3.abs, r1.abs ; ldunif" },
{ 42, 0x481edcd6b3184500ull, "vfmin.norn log, r4.hh, r0 ; fmul.ifnb rf51, rf20.abs, r0.l" },
{ 42, 0x041618d57c453000ull, "shl.andn exp, r3, r2 ; add.ifb rf35, r1, r2" },
{ 42, 0x7048e5da49272800ull, "fsub.ifa rf26, r2.l, rf32 ; fmul.pushc sin, r1.h, r1.abs; ldunif" },
/* v4.1 signals */
{ 41, 0x1f010520cf60a000ull, "fcmp.andz rf32, r2.h, r1.h ; vfmul rf20, r0.hh, r3 ; ldunifa" },
{ 41, 0x932045e6c16ea000ull, "fcmp rf38, r2.abs, r5 ; fmul rf23.l, r3, r3.abs ; ldunifarf.rf1" },
{ 41, 0xd72f0434e43ae5c0ull, "fcmp rf52.h, rf23, r5.abs ; fmul rf16.h, rf23, r1 ; ldunifarf.rf60" },
{ 41, 0xdb3048eb9d533780ull, "fmax rf43.l, r3.h, rf30 ; fmul rf35.h, r4, r2.l ; ldunifarf.r1" },
{ 41, 0x733620471e6ce700ull, "faddnf rf7.l, rf28.h, r1.l ; fmul r1, r3.h, r3.abs ; ldunifarf.rsqrt2" },
{ 41, 0x9c094adef634b000ull, "ffloor.ifb rf30.l, r3 ; fmul.pushz rf43.l, r5, r1.h" },
/* signals */
{ 42, 0x1f010520cf60a000ull, "fcmp.andz rf32, r2.h, r1.h ; vfmul rf20, r0.hh, r3 ; ldunifa" },
{ 42, 0x932045e6c16ea000ull, "fcmp rf38, r2.abs, r5 ; fmul rf23.l, r3, r3.abs ; ldunifarf.rf1" },
{ 42, 0xd72f0434e43ae5c0ull, "fcmp rf52.h, rf23, r5.abs ; fmul rf16.h, rf23, r1 ; ldunifarf.rf60" },
{ 42, 0xdb3048eb9d533780ull, "fmax rf43.l, r3.h, rf30 ; fmul rf35.h, r4, r2.l ; ldunifarf.r1" },
{ 42, 0x733620471e6ce700ull, "faddnf rf7.l, rf28.h, r1.l ; fmul r1, r3.h, r3.abs ; ldunifarf.rsqrt2" },
{ 42, 0x9c094adef634b000ull, "ffloor.ifb rf30.l, r3 ; fmul.pushz rf43.l, r5, r1.h" },
/* v4.1 opcodes */
{ 41, 0x3de020c7bdfd200dull, "ldvpmg_in rf7, r2, r2 ; mov r3, 13" },
{ 41, 0x3de02040f8ff7201ull, "stvpmv 1, rf8 ; mov r1, 1" },
{ 41, 0xd8000e50bb2d3000ull, "sampid rf16 ; fmul rf57.h, r3, r1.l" },
/* opcodes */
{ 42, 0x3de020c7bdfd200dull, "ldvpmg_in rf7, r2, r2 ; mov r3, 13" },
{ 42, 0x3de02040f8ff7201ull, "stvpmv 1, rf8 ; mov r1, 1" },
{ 42, 0xd8000e50bb2d3000ull, "sampid rf16 ; fmul rf57.h, r3, r1.l" },
/* v4.1 SFU instructions. */
{ 41, 0xe98d60c1ba2aef80ull, "recip rf1, rf62 ; fmul r3.h, r2.l, r1.l ; ldunifrf.rf53" },
{ 41, 0x7d87c2debc51c000ull, "rsqrt rf30, r4 ; fmul rf11, r4.h, r2.h ; ldunifrf.rf31" },
{ 41, 0xb182475abc2bb000ull, "rsqrt2 rf26, r3 ; fmul rf29.l, r2.h, r1.abs ; ldunifrf.rf9" },
{ 41, 0x79880808bc0b6900ull, "sin rf8, rf36 ; fmul rf32, r2.h, r0.l ; ldunifrf.rf32" },
{ 41, 0x04092094bc5a28c0ull, "exp.ifb rf20, r2 ; add r2, rf35, r2" },
{ 41, 0xe00648bfbc32a000ull, "log rf63, r2 ; fmul.andnn rf34.h, r4.l, r1.abs" },
/* SFU instructions. */
{ 42, 0xe98d60c1ba2aef80ull, "recip rf1, rf62 ; fmul r3.h, r2.l, r1.l ; ldunifrf.rf53" },
{ 42, 0x7d87c2debc51c000ull, "rsqrt rf30, r4 ; fmul rf11, r4.h, r2.h ; ldunifrf.rf31" },
{ 42, 0xb182475abc2bb000ull, "rsqrt2 rf26, r3 ; fmul rf29.l, r2.h, r1.abs ; ldunifrf.rf9" },
{ 42, 0x79880808bc0b6900ull, "sin rf8, rf36 ; fmul rf32, r2.h, r0.l ; ldunifrf.rf32" },
{ 42, 0x04092094bc5a28c0ull, "exp.ifb rf20, r2 ; add r2, rf35, r2" },
{ 42, 0xe00648bfbc32a000ull, "log rf63, r2 ; fmul.andnn rf34.h, r4.l, r1.abs" },
/* v4.2 changes */
/* barrierid */
{ 42, 0x3c203192bb814000ull, "barrierid syncb ; nop ; thrsw" },
};