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radeonsi: implement resource_get_address

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Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35175>
This commit is contained in:
Karol Herbst
2024-09-23 12:58:59 +02:00
committed by Marge Bot
parent a1b8c6c404
commit a107041112
4 changed files with 24 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
docs/features.txt
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@@ -854,7 +854,7 @@ Rusticl extensions that are not part of any OpenCL version:
cl_khr_terminate_context not started
cl_khr_throttle_hints not started
cl_khr_work_group_uniform_arithmetic not started
cl_ext_buffer_device_address DONE (iris, llvmpipe, zink)
cl_ext_buffer_device_address DONE (iris, llvmpipe, radeonsi, zink)
cl_arm_non_uniform_work_group_size not started
cl_arm_shared_virtual_memory in progress (nvc0)
cl_intel_required_subgroup_size in progress (available with RUSTICL_FEATURES=intel)

2
docs/relnotes/new_features.txt
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@@ -27,7 +27,7 @@ VK_EXT_image_2d_view_of_3d on panvk
VK_EXT_texel_buffer_alignment on panvk
cl_khr_kernel_clock on freedreno, iris, llvmpipe, nvc0, panfrost, radeonsi and zink with llvm-19 or newer
GL_KHR_texture_compression_astc_hdr on panfrost and asahi
cl_ext_buffer_device_address on iris, llvmpipe and zink
cl_ext_buffer_device_address on iris, llvmpipe, radeonsi and zink
Completed OpenCL 2.0 coarse grain buffer SVM support for iris
VK_EXT_shader_subgroup_ballot on panvk
VK_EXT_shader_subgroup_vote on panvk

13
src/gallium/drivers/radeonsi/si_buffer.c
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@@ -256,6 +256,11 @@ static bool si_invalidate_buffer(struct si_context *sctx, struct si_resource *bu
if (buf->b.is_user_ptr)
return false;
/* Can't reallocate when this resource can't change its address.
*/
if (buf->b.b.flags & PIPE_RESOURCE_FLAG_FIXED_ADDRESS)
return false;
/* Check if mapping this buffer would cause waiting for the GPU. */
if (!si_is_buffer_idle(sctx, buf, RADEON_USAGE_READWRITE)) {
/* Reallocate the buffer in the same pipe_resource. */
@@ -776,11 +781,19 @@ static bool si_resource_commit(struct pipe_context *pctx, struct pipe_resource *
return si_texture_commit(ctx, res, level, box, commit);
}
static uint64_t si_resource_get_address(struct pipe_screen *screen,
struct pipe_resource *resource)
{
struct si_resource *res = si_resource(resource);
return res->gpu_address;
}
void si_init_screen_buffer_functions(struct si_screen *sscreen)
{
sscreen->b.resource_create = si_resource_create;
sscreen->b.resource_destroy = si_resource_destroy;
sscreen->b.resource_from_user_memory = si_buffer_from_user_memory;
sscreen->b.resource_get_address = si_resource_get_address;
}
void si_init_buffer_functions(struct si_context *sctx)

9
src/gallium/drivers/radeonsi/si_compute.c
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@@ -968,6 +968,15 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RW_BUFFER);
}
for (unsigned i = 0; i < info->num_globals; i++) {
struct si_resource *buffer = si_resource(info->globals[i]);
if (!buffer) {
continue;
}
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, buffer,
RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RW_BUFFER);
}
/* Registers that are not read from memory should be set before this: */
si_emit_barrier_direct(sctx);