anv: Make shaders array in anv_graphics_pipeline fit Task/Mesh
We could decouple the locations in the array from the gl_shader_stage enum values, but for now this is convenient. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13637>
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@@ -1409,7 +1409,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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int64_t pipeline_start = os_time_get_nano();
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const struct brw_compiler *compiler = pipeline->base.device->physical->compiler;
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struct anv_pipeline_stage stages[MESA_SHADER_STAGES] = {};
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struct anv_pipeline_stage stages[ANV_GRAPHICS_SHADER_STAGE_COUNT] = {};
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/* Information on which states are considered dynamic. */
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const VkPipelineDynamicStateCreateInfo *dyn_info =
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@@ -1655,8 +1655,8 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
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* used in all the active shaders, so this check can't be done per
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* individual shaders.
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*/
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nir_shader *shaders[MESA_SHADER_STAGES] = {};
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for (unsigned s = 0; s < MESA_SHADER_STAGES; s++)
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nir_shader *shaders[ANV_GRAPHICS_SHADER_STAGE_COUNT] = {};
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for (unsigned s = 0; s < ARRAY_SIZE(shaders); s++)
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shaders[s] = stages[s].nir;
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pipeline->use_primitive_replication =
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@@ -245,6 +245,8 @@ struct intel_perf_query_result;
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*/
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#define ANV_PERF_QUERY_OFFSET_REG 0x2670 /* MI_ALU_REG14 */
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#define ANV_GRAPHICS_SHADER_STAGE_COUNT (MESA_SHADER_MESH + 1)
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/* For gfx12 we set the streamout buffers using 4 separate commands
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* (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
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* of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
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@@ -3554,7 +3556,7 @@ struct anv_graphics_pipeline {
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struct anv_subpass * subpass;
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struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
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struct anv_shader_bin * shaders[ANV_GRAPHICS_SHADER_STAGE_COUNT];
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VkShaderStageFlags active_stages;
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