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i965/fs: Use the GRF for UNTYPED_SURFACE_READ instructions

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Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand
2014-09-11 16:43:37 -07:00
parent d25aaf1cb1
commit 9e1f52a6e2
4 changed files with 24 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_fs.cpp
+3
View File
@@ -508,6 +508,7 @@ fs_inst::is_send_from_grf() const
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
return true;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
return src[1].file == GRF;
@@ -916,6 +917,8 @@ fs_inst::regs_read(fs_visitor *v, int arg) const
return mlen;
} else if (opcode == SHADER_OPCODE_UNTYPED_ATOMIC && arg == 0) {
return mlen;
} else if (opcode == SHADER_OPCODE_UNTYPED_SURFACE_READ && arg == 0) {
return mlen;
}
switch (src[arg].file) {
src/mesa/drivers/dri/i965/brw_fs.h
+1
View File
@@ -749,6 +749,7 @@ private:
void generate_untyped_surface_read(fs_inst *inst,
struct brw_reg dst,
struct brw_reg payload,
struct brw_reg surf_index);
bool patch_discard_jumps_to_fb_writes();
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+4 -3
View File
@@ -1489,14 +1489,15 @@ fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
void
fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
struct brw_reg payload,
struct brw_reg surf_index)
{
assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
surf_index.type == BRW_REGISTER_TYPE_UD);
brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
brw_untyped_surface_read(p, dst, payload,
surf_index.dw1.ud,
inst->mlen, dispatch_width / 8);
inst->mlen, inst->exec_size / 8);
brw_mark_surface_used(prog_data, surf_index.dw1.ud);
}
@@ -1902,7 +1903,7 @@ fs_generator::generate_code(const cfg_t *cfg)
break;
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
generate_untyped_surface_read(inst, dst, src[0]);
generate_untyped_surface_read(inst, dst, src[0], src[1]);
break;
case FS_OPCODE_SET_SIMD4X2_OFFSET:
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+16 -13
View File
@@ -2785,34 +2785,37 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
bool uses_kill =
(stage == MESA_SHADER_FRAGMENT) &&
((brw_wm_prog_data*) this->prog_data)->uses_kill;
const unsigned operand_len = dispatch_width / 8;
unsigned mlen = 0;
fs_inst *inst;
int reg_width = dispatch_width / 8;
fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
sources[0] = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
/* Initialize the sample mask in the message header. */
emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
emit(MOV(sources[0], fs_reg(0u)))
->force_writemask_all = true;
if (uses_kill) {
emit(MOV(brw_uvec_mrf(1, mlen, 7), brw_flag_reg(0, 1)))
emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
->force_writemask_all = true;
} else {
emit(MOV(brw_uvec_mrf(1, mlen, 7),
emit(MOV(component(sources[0], 7),
retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
->force_writemask_all = true;
}
mlen++;
/* Set the surface read offset. */
emit(MOV(brw_uvec_mrf(dispatch_width, mlen, 0), offset));
mlen += operand_len;
sources[1] = fs_reg(this, glsl_type::uint_type);
emit(MOV(sources[1], offset));
int mlen = 1 + reg_width;
fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(mlen),
BRW_REGISTER_TYPE_UD);
fs_inst *inst = emit(LOAD_PAYLOAD(src_payload, sources, 2));
/* Emit the instruction. */
inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst, fs_reg(surf_index));
inst->base_mrf = 0;
inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst, src_payload,
fs_reg(surf_index));
inst->mlen = mlen;
inst->header_present = true;
}
fs_inst *