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i965/vs: Fix point size handling on gen4.

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Fixes glsl-vs-point-size.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt
2011-08-30 15:34:43 -07:00
parent 9367960ea6
commit 9bd8d90646
1 changed files with 5 additions and 4 deletions
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src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+5 -4
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@@ -1748,14 +1748,15 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
emit(MOV(header1, 0u));
if (c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) {
assert(!"finishme: psiz");
src_reg psiz;
src_reg psiz = src_reg(output_reg[VERT_RESULT_PSIZ]);
current_annotation = "Point size";
header1.writemask = WRITEMASK_W;
emit(MUL(header1, psiz, 1u << 11));
emit(MUL(header1, psiz, src_reg((float)(1 << 11))));
emit(AND(header1, src_reg(header1), 0x7ff << 8));
}
current_annotation = "Clipping flags";
for (i = 0; i < c->key.nr_userclip; i++) {
vec4_instruction *inst;
@@ -1792,7 +1793,7 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
}
header1.writemask = WRITEMASK_XYZW;
emit(MOV(reg, src_reg(header1)));
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1)));
} else if (intel->gen < 6) {
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u));
} else {