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ac/gpu_info: add has_2d_tiling

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2018-05-02 19:54:35 -04:00
parent d26696283d
commit 9b1fdfc541
4 changed files with 6 additions and 5 deletions
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src/amd/common/ac_gpu_info.c
+2
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@@ -337,6 +337,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->has_sparse_vm_mappings =
info->chip_class >= CIK && info->chip_class <= VI &&
info->drm_minor >= 13;
info->has_2d_tiling = true;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
@@ -496,6 +497,7 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
src/amd/common/ac_gpu_info.h
+1
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@@ -108,6 +108,7 @@ struct radeon_info {
bool has_indirect_compute_dispatch;
bool has_unaligned_shader_loads;
bool has_sparse_vm_mappings;
bool has_2d_tiling;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
src/gallium/drivers/radeonsi/si_get.c
+1 -5
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@@ -198,11 +198,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
sscreen->info.has_gpu_reset_counter_query;
case PIPE_CAP_TEXTURE_MULTISAMPLE:
/* 2D tiling on CIK is supported since DRM 2.35.0 */
return sscreen->info.chip_class < CIK ||
(sscreen->info.drm_major == 2 &&
sscreen->info.drm_minor >= 35) ||
sscreen->info.drm_major == 3;
return sscreen->info.has_2d_tiling;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return SI_MAP_BUFFER_ALIGNMENT;
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+2
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@@ -548,6 +548,8 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
ws->info.drm_minor >= 50;
ws->info.has_sparse_vm_mappings = false;
/* 2D tiling on CIK is supported since DRM 2.35.0 */
ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;