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radv: fix indirect dispatches on compute queue with conditional rendering on GFX7

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COND_EXEC needs to happen right before PKT3_DISPATCH_INDIRECT.

Like this combination will probably never happen but better to have
it fixed anyways.

Fixes: 5c03cdbd02 ("radv: fix indirect dispatches on the compute queue on GFX7")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27655>
This commit is contained in:
Samuel Pitoiset
2024-02-16 14:05:05 +01:00
committed by Marge Bot
parent 776f4523f9
commit 9ae8f0f9d7
1 changed files with 7 additions and 3 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+7 -3
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@@ -10055,12 +10055,16 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv
if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
uint64_t indirect_va = info->va;
const bool needs_align32_workaround =
cmd_buffer->device->physical_device->rad_info.has_async_compute_align32_bug &&
cmd_buffer->qf == RADV_QUEUE_COMPUTE && !radv_is_aligned(indirect_va, 32);
const unsigned ace_predication_size =
4 /* DISPATCH_INDIRECT */ + (needs_align32_workaround ? 6 * 3 /* 3x COPY_DATA */ : 0);
radv_cs_emit_compute_predication(&cmd_buffer->state, cs, cmd_buffer->mec_inv_pred_va,
&cmd_buffer->mec_inv_pred_emitted, 4 /* DISPATCH_INDIRECT size */);
&cmd_buffer->mec_inv_pred_emitted, ace_predication_size);
if (cmd_buffer->device->physical_device->rad_info.has_async_compute_align32_bug &&
cmd_buffer->qf == RADV_QUEUE_COMPUTE && !radv_is_aligned(indirect_va, 32)) {
if (needs_align32_workaround) {
const uint64_t unaligned_va = indirect_va;
UNUSED void *ptr;
uint32_t offset;