From 9ae8f0f9d7444cd54d817bb2bfff59b8fd6e543f Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 16 Feb 2024 14:05:05 +0100 Subject: [PATCH] radv: fix indirect dispatches on compute queue with conditional rendering on GFX7 COND_EXEC needs to happen right before PKT3_DISPATCH_INDIRECT. Like this combination will probably never happen but better to have it fixed anyways. Fixes: 5c03cdbd02a ("radv: fix indirect dispatches on the compute queue on GFX7") Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 506d5e0a640..0d7c2c332e4 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -10055,12 +10055,16 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv if (radv_cmd_buffer_uses_mec(cmd_buffer)) { uint64_t indirect_va = info->va; + const bool needs_align32_workaround = + cmd_buffer->device->physical_device->rad_info.has_async_compute_align32_bug && + cmd_buffer->qf == RADV_QUEUE_COMPUTE && !radv_is_aligned(indirect_va, 32); + const unsigned ace_predication_size = + 4 /* DISPATCH_INDIRECT */ + (needs_align32_workaround ? 6 * 3 /* 3x COPY_DATA */ : 0); radv_cs_emit_compute_predication(&cmd_buffer->state, cs, cmd_buffer->mec_inv_pred_va, - &cmd_buffer->mec_inv_pred_emitted, 4 /* DISPATCH_INDIRECT size */); + &cmd_buffer->mec_inv_pred_emitted, ace_predication_size); - if (cmd_buffer->device->physical_device->rad_info.has_async_compute_align32_bug && - cmd_buffer->qf == RADV_QUEUE_COMPUTE && !radv_is_aligned(indirect_va, 32)) { + if (needs_align32_workaround) { const uint64_t unaligned_va = indirect_va; UNUSED void *ptr; uint32_t offset;