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amd,radv,radeonsi: add ac_emit_cp_gfx_scratch()

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
This commit is contained in:
Samuel Pitoiset
2025-10-14 12:32:54 +02:00
committed by Marge Bot
parent 9ff8e71b4e
commit 9ad7fb8569
4 changed files with 33 additions and 24 deletions
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18
src/amd/common/ac_cmdbuf.c
View File

@@ -1174,3 +1174,21 @@ ac_emit_cp_tess_rings(struct ac_cmdbuf *cs, const struct radeon_info *info,
ac_cmdbuf_end();
}
void
ac_emit_cp_gfx_scratch(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level,
uint64_t va, uint32_t size)
{
ac_cmdbuf_begin(cs);
if (gfx_level >= GFX11) {
ac_cmdbuf_set_context_reg_seq(R_0286E8_SPI_TMPRING_SIZE, 3);
ac_cmdbuf_emit(size);
ac_cmdbuf_emit(va >> 8);
ac_cmdbuf_emit(va >> 40);
} else {
ac_cmdbuf_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, size);
}
ac_cmdbuf_end();
}

9
src/amd/common/ac_cmdbuf.h
View File

@@ -81,6 +81,11 @@ struct ac_cmdbuf {
#define ac_cmdbuf_set_uconfig_reg(reg, value) __ac_cmdbuf_set_reg(reg, 0, value, CIK_UCONFIG, PKT3_SET_UCONFIG_REG)
/* Packet building helpers for CONTEXT registers. */
#define ac_cmdbuf_set_context_reg_seq(reg, num) __ac_cmdbuf_set_reg_seq(reg, num, 0, SI_CONTEXT, PKT3_SET_CONTEXT_REG, 0)
#define ac_cmdbuf_set_context_reg(reg, value) __ac_cmdbuf_set_reg(reg, 0, value, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
struct ac_preamble_state {
uint64_t border_color_va;
@@ -151,6 +156,10 @@ void
ac_emit_cp_tess_rings(struct ac_cmdbuf *cs, const struct radeon_info *info,
uint64_t va);
void
ac_emit_cp_gfx_scratch(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level,
uint64_t va, uint32_t size);
#ifdef __cplusplus
}
#endif

17
src/amd/vulkan/radv_queue.c
View File

@@ -460,24 +460,13 @@ radv_emit_graphics_scratch(struct radv_device *device, struct radv_cmd_stream *c
if (!scratch_bo)
return;
const uint64_t va = radv_buffer_get_va(scratch_bo);
ac_get_scratch_tmpring_size(gpu_info, waves, size_per_wave, &tmpring_size);
radv_cs_add_buffer(device->ws, cs->b, scratch_bo);
radeon_begin(cs);
if (gpu_info->gfx_level >= GFX11) {
uint64_t va = radv_buffer_get_va(scratch_bo);
radeon_set_context_reg_seq(R_0286E8_SPI_TMPRING_SIZE, 3);
radeon_emit(tmpring_size);
radeon_emit(va >> 8); /* SPI_GFX_SCRATCH_BASE_LO */
radeon_emit(va >> 40); /* SPI_GFX_SCRATCH_BASE_HI */
} else {
radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, tmpring_size);
}
radeon_end();
ac_emit_cp_gfx_scratch(cs->b, pdev->info.gfx_level, va, tmpring_size);
}
static void

13
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View File

@@ -4518,16 +4518,9 @@ static void si_emit_scratch_state(struct si_context *sctx, unsigned index)
{
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
radeon_begin(cs);
if (sctx->gfx_level >= GFX11) {
radeon_set_context_reg_seq(R_0286E8_SPI_TMPRING_SIZE, 3);
radeon_emit(sctx->spi_tmpring_size); /* SPI_TMPRING_SIZE */
radeon_emit(sctx->scratch_buffer->gpu_address >> 8); /* SPI_GFX_SCRATCH_BASE_LO */
radeon_emit(sctx->scratch_buffer->gpu_address >> 40); /* SPI_GFX_SCRATCH_BASE_HI */
} else {
radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
}
radeon_end();
ac_emit_cp_gfx_scratch(&cs->current, sctx->gfx_level,
sctx->scratch_buffer->gpu_address,
sctx->spi_tmpring_size);
if (sctx->scratch_buffer) {
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->scratch_buffer,