i965/gs: Add GS_OPCODE_URB_WRITE.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

src/mesa/drivers/dri/i965/brw_defines.h

@@ -799,6 +799,15 @@ enum opcode {
    VS_OPCODE_PULL_CONSTANT_LOAD,
    VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
    VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
+
+   /**
+    * Write geometry shader output data to the URB.
+    *
+    * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
+    * R0 to the first MRF.  This allows the geometry shader to override the
+    * "Slot {0,1} Offset" fields in the message header.
+    */
+   GS_OPCODE_URB_WRITE,
 };
 
 #define BRW_PREDICATE_NONE             0

src/mesa/drivers/dri/i965/brw_shader.cpp

@@ -485,7 +485,7 @@ brw_instruction_name(enum opcode op)
       return "placeholder_halt";
 
    case VS_OPCODE_URB_WRITE:
-      return "urb_write";
+      return "vs_urb_write";
    case VS_OPCODE_SCRATCH_READ:
       return "scratch_read";
    case VS_OPCODE_SCRATCH_WRITE:
@@ -497,6 +497,9 @@ brw_instruction_name(enum opcode op)
    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
       return "unpack_flags_simd4x2";
 
+   case GS_OPCODE_URB_WRITE:
+      return "gs_urb_write";
+
    default:
       /* Yes, this leaks.  It's in debug code, it should never occur, and if
        * it does, you should just add the case to the list above.

src/mesa/drivers/dri/i965/brw_vec4.cpp

@@ -259,6 +259,8 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
       return 2;
    case VS_OPCODE_SCRATCH_WRITE:
       return 3;
+   case GS_OPCODE_URB_WRITE:
+      return 0;
    case SHADER_OPCODE_SHADER_TIME_ADD:
       return 0;
    case SHADER_OPCODE_TEX:

src/mesa/drivers/dri/i965/brw_vec4.h

@@ -627,7 +627,8 @@ private:
 		     struct brw_reg dst,
 		     struct brw_reg src);
 
-   void generate_urb_write(vec4_instruction *inst);
+   void generate_vs_urb_write(vec4_instruction *inst);
+   void generate_gs_urb_write(vec4_instruction *inst);
    void generate_oword_dual_block_offsets(struct brw_reg m1,
 					  struct brw_reg index);
    void generate_scratch_write(vec4_instruction *inst,

src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

@@ -399,7 +399,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 }
 
 void
-vec4_generator::generate_urb_write(vec4_instruction *inst)
+vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
 {
    brw_urb_WRITE(p,
 		 brw_null_reg(), /* dest */
@@ -412,6 +412,21 @@ vec4_generator::generate_urb_write(vec4_instruction *inst)
 		 BRW_URB_SWIZZLE_INTERLEAVE);
 }
 
+void
+vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
+{
+   struct brw_reg src = brw_message_reg(inst->base_mrf);
+   brw_urb_WRITE(p,
+                 brw_null_reg(), /* dest */
+                 inst->base_mrf, /* starting mrf reg nr */
+                 src,
+                 inst->urb_write_flags,
+                 inst->mlen,
+                 0,             /* response len */
+                 inst->offset,  /* urb destination offset */
+                 BRW_URB_SWIZZLE_INTERLEAVE);
+}
+
 void
 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
                                                   struct brw_reg index)
@@ -861,7 +876,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
       break;
 
    case VS_OPCODE_URB_WRITE:
-      generate_urb_write(inst);
+      generate_vs_urb_write(inst);
       break;
 
    case VS_OPCODE_SCRATCH_READ:
@@ -880,6 +895,10 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
       generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
       break;
 
+   case GS_OPCODE_URB_WRITE:
+      generate_gs_urb_write(inst);
+      break;
+
    case SHADER_OPCODE_SHADER_TIME_ADD:
       brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
       mark_surface_used(SURF_INDEX_VS_SHADER_TIME);