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radv: fix VRS subpass attachments with mipmaps

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On GFX10.3, the driver should use the VRS image view provided by the
rendering state because it sets the base level correctly. On GFX11+,
using the image view dimension is enough.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29531>
This commit is contained in:
Samuel Pitoiset
2024-06-04 16:41:31 +02:00
committed by Marge Bot
parent 9f22b31ce8
commit 964f2b8140
3 changed files with 9 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/meta/radv_meta.h
+1 -1
View File
@@ -229,7 +229,7 @@ void radv_decompress_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *
void radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image);
void radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
const VkImageSubresourceRange *subresourceRange);
void radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image, const VkRect2D *rect,
void radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *vrs_iview, const VkRect2D *rect,
struct radv_image *dst_image, struct radv_buffer *htile_buffer, bool read_htile_value);
bool radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_image,
src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c
+2 -19
View File
@@ -172,13 +172,12 @@ fail:
}
void
radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image, const VkRect2D *rect,
radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *vrs_iview, const VkRect2D *rect,
struct radv_image *dst_image, struct radv_buffer *htile_buffer, bool read_htile_value)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radv_meta_state *state = &device->meta_state;
struct radv_meta_saved_state saved_state;
struct radv_image_view vrs_iview;
assert(radv_image_has_htile(dst_image));
@@ -200,20 +199,6 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
state->copy_vrs_htile_pipeline);
radv_image_view_init(&vrs_iview, device,
&(VkImageViewCreateInfo){
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(vrs_image),
.viewType = VK_IMAGE_VIEW_TYPE_2D,
.format = vrs_image->vk.format,
.subresourceRange = {.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
.baseMipLevel = 0,
.levelCount = 1,
.baseArrayLayer = 0,
.layerCount = 1},
},
0, NULL);
radv_meta_push_descriptor_set(
cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, state->copy_vrs_htile_p_layout, 0, /* set */
2, /* descriptorWriteCount */
@@ -226,7 +211,7 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i
(VkDescriptorImageInfo[]){
{
.sampler = VK_NULL_HANDLE,
.imageView = radv_image_view_to_handle(&vrs_iview),
.imageView = radv_image_view_to_handle(vrs_iview),
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
},
}},
@@ -255,8 +240,6 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i
radv_unaligned_dispatch(cmd_buffer, width, height, 1);
radv_image_view_finish(&vrs_iview);
radv_meta_restore(&saved_state, cmd_buffer);
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
src/amd/vulkan/radv_cmd_buffer.c
+6 -5
View File
@@ -4763,13 +4763,14 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
uint64_t va = 0;
if (vrs_surface_enable) {
struct radv_image *vrs_image = render->vrs_att.iview->image;
const struct radv_image_view *vrs_iview = render->vrs_att.iview;
struct radv_image *vrs_image = vrs_iview->image;
va = radv_buffer_get_va(vrs_image->bindings[0].bo) + vrs_image->bindings[0].offset;
va |= vrs_image->planes[0].surface.tile_swizzle << 8;
xmax = vrs_image->vk.extent.width - 1;
ymax = vrs_image->vk.extent.height - 1;
xmax = vrs_iview->vk.extent.width - 1;
ymax = vrs_iview->vk.extent.height - 1;
}
radeon_set_context_reg_seq(cmd_buffer->cs, R_0283F0_PA_SC_VRS_RATE_BASE, 3);
@@ -9432,7 +9433,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
render->area.offset.x + render->area.extent.height <= ds_image->vk.extent.height);
/* Copy the VRS rates to the HTILE buffer. */
radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview->image, &render->area, ds_image, &htile_buffer, true);
radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview, &render->area, ds_image, &htile_buffer, true);
radv_buffer_finish(&htile_buffer);
} else {
@@ -9451,7 +9452,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
area.extent.height = MIN2(area.extent.height, ds_image->vk.extent.height - area.offset.y);
/* Copy the VRS rates to the HTILE buffer. */
radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview->image, &area, ds_image, htile_buffer, false);
radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview, &area, ds_image, htile_buffer, false);
}
}
}