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i956: Add a function to load a 64-bit register from a buffer

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Adds brw_load_register_mem64 which is similar to brw_load_register_mem
except that it queues two GEN7_MI_LOAD_REGISTER_MEM commands in order
to load both halves of a 64-bit register. The function is implemented
by splitting the 32-bit version into an internal helper function which
takes a size.

This will later be used to set the 64-bit predicate source registers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Neil Roberts
2015-05-11 14:00:42 +01:00
parent 8a59f2f26f
commit 9585879d46
2 changed files with 48 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_context.h
+5
View File
@@ -1606,6 +1606,11 @@ void brw_load_register_mem(struct brw_context *brw,
drm_intel_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
void brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
drm_intel_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
/*======================================================================
* brw_state_dump.c
src/mesa/drivers/dri/i965/intel_batchbuffer.c
+43 -16
View File
@@ -743,6 +743,38 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw)
brw_render_cache_set_clear(brw);
}
static void
load_sized_register_mem(struct brw_context *brw,
uint32_t reg,
drm_intel_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset,
int size)
{
int i;
/* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
assert(brw->gen >= 7);
if (brw->gen >= 8) {
BEGIN_BATCH(4 * size);
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg + i * 4);
OUT_RELOC64(bo, read_domains, write_domain, offset + i * 4);
}
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3 * size);
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + i * 4);
OUT_RELOC(bo, read_domains, write_domain, offset + i * 4);
}
ADVANCE_BATCH();
}
}
void
brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
@@ -750,20 +782,15 @@ brw_load_register_mem(struct brw_context *brw,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset)
{
/* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
assert(brw->gen >= 7);
if (brw->gen >= 8) {
BEGIN_BATCH(4);
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg);
OUT_RELOC64(bo, read_domains, write_domain, offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
OUT_RELOC(bo, read_domains, write_domain, offset);
ADVANCE_BATCH();
}
load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 1);
}
void
brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
drm_intel_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset)
{
load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 2);
}