aco: remove p_v_cvt_pk_u8_f32

Now unused.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35391>

src/amd/compiler/aco_ir.cpp

@@ -454,8 +454,7 @@ can_use_DPP(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, bool dpp
           instr->opcode != aco_opcode::v_permlanex16_b32 &&
           instr->opcode != aco_opcode::v_permlane64_b32 &&
           instr->opcode != aco_opcode::v_readlane_b32_e64 &&
-          instr->opcode != aco_opcode::v_writelane_b32_e64 &&
-          instr->opcode != aco_opcode::p_v_cvt_pk_u8_f32;
+          instr->opcode != aco_opcode::v_writelane_b32_e64;
 }
 
 aco_ptr<Instruction>

src/amd/compiler/aco_lower_to_hw_instr.cpp

@@ -2928,14 +2928,6 @@ lower_to_hw_instr(Program* program)
             ctx.instructions.emplace_back(std::move(instr));
 
             emit_set_mode(bld, block->fp_mode, set_round, false);
-         } else if (instr->opcode == aco_opcode::p_v_cvt_pk_u8_f32) {
-            Definition def = instr->definitions[0];
-            VALU_instruction& valu =
-               bld.vop3(aco_opcode::v_cvt_pk_u8_f32, def, instr->operands[0],
-                        Operand::c32(def.physReg().byte()), Operand(def.physReg(), v1))
-                  ->valu();
-            valu.abs = instr->valu().abs;
-            valu.neg = instr->valu().neg;
          } else if (instr->isMIMG() && instr->mimg().strict_wqm) {
             lower_image_sample(&ctx, instr);
             ctx.instructions.emplace_back(std::move(instr));

src/amd/compiler/aco_opcodes.py

@@ -1306,7 +1306,6 @@ VOP3 = {
    ("v_sad_u16",               dst(U32), src(U32, U32, U32), op(0x15c, gfx8=0x1db, gfx10=0x15c, gfx11=0x224)),
    ("v_sad_u32",               dst(U32), src(U32, U32, U32), op(0x15d, gfx8=0x1dc, gfx10=0x15d, gfx11=0x225)),
    ("v_cvt_pk_u8_f32",         dst(U32), src(F32, U32, U32), op(0x15e, gfx8=0x1dd, gfx10=0x15e, gfx11=0x226)),
-   ("p_v_cvt_pk_u8_f32",       dst(U32), src(F32), op(-1)),
    ("v_div_fixup_f32",         dst(F32), src(F32, F32, F32), op(0x15f, gfx8=0x1de, gfx10=0x15f, gfx11=0x227)),
    ("v_div_fixup_f64",         dst(F64), src(F64, F64, F64), op(0x160, gfx8=0x1df, gfx10=0x160, gfx11=0x228)),
    ("v_lshl_b64",              dst(U64), src(U64, U32), op(0x161, gfx8=-1), InstrClass.Valu64),

src/amd/compiler/aco_register_allocation.cpp

@@ -694,7 +694,7 @@ DefInfo::get_subdword_definition_info(Program* program, const aco_ptr<Instructio
    if (instr->isVALU()) {
       assert(rc.bytes() <= 2);
 
-      if (can_use_SDWA(gfx_level, instr, false) || instr->opcode == aco_opcode::p_v_cvt_pk_u8_f32)
+      if (can_use_SDWA(gfx_level, instr, false))
          return;
 
       rc = instr_is_16bit(gfx_level, instr->opcode) ? v2b : v1;
@@ -771,9 +771,6 @@ add_subdword_definition(Program* program, aco_ptr<Instruction>& instr, PhysReg r
       amd_gfx_level gfx_level = program->gfx_level;
       assert(instr->definitions[0].bytes() <= 2);
 
-      if (instr->opcode == aco_opcode::p_v_cvt_pk_u8_f32)
-         return;
-
       if (reg.byte() == 0 && allow_16bit_write && instr_is_16bit(gfx_level, instr->opcode))
          return;
 

src/amd/compiler/aco_validate.cpp

@@ -1270,7 +1270,6 @@ validate_subdword_definition(amd_gfx_level gfx_level, const aco_ptr<Instruction>
    case aco_opcode::global_load_short_d16_hi:
    case aco_opcode::ds_read_u8_d16_hi:
    case aco_opcode::ds_read_u16_d16_hi: return byte == 2;
-   case aco_opcode::p_v_cvt_pk_u8_f32: return true;
    default: break;
    }
 
@@ -1287,8 +1286,6 @@ get_subdword_bytes_written(Program* program, const aco_ptr<Instruction>& instr,
       return gfx_level >= GFX8 ? def.bytes() : def.size() * 4u;
    if (instr->isVALU() || instr->isVINTRP()) {
       assert(def.bytes() <= 2);
-      if (instr->opcode == aco_opcode::p_v_cvt_pk_u8_f32)
-         return 1;
 
       if (instr->isSDWA())
          return instr->sdwa().dst_sel.size();