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@@ -0,0 +1,441 @@
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/*
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* Copyright (C) 2017-2018 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#define GPU 600
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#include "ir3_context.h"
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#include "ir3_image.h"
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/*
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* Handlers for instructions changed/added in a6xx:
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*
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* Starting with a6xx, isam and stbi is used for SSBOs as well; stbi and the
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* atomic instructions (used for both SSBO and image) use a new instruction
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* encoding compared to a4xx/a5xx.
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*/
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static struct ir3_instruction *
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ssbo_offset(struct ir3_block *b, struct ir3_instruction *byte_offset)
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{
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/* TODO hardware wants offset in terms of elements, not bytes. Which
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* is kinda nice but opposite of what nir does. It would be nice if
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* we had a way to request the units of the offset to avoid the extra
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* shift instructions..
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*/
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return ir3_SHR_B(b, byte_offset, 0, create_immed(b, 2), 0);
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}
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/* src[] = { buffer_index, offset }. No const_index */
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static void
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emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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struct ir3_instruction **dst)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *offset;
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struct ir3_instruction *sam;
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nir_const_value *buffer_index;
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/* can this be non-const buffer_index? how do we handle that? */
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buffer_index = nir_src_as_const_value(intr->src[0]);
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compile_assert(ctx, buffer_index);
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int tex_idx = ir3_ssbo_to_tex(&ctx->so->image_mapping, buffer_index->u32[0]);
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offset = ssbo_offset(b, ir3_get_src(ctx, &intr->src[1])[0]);
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/* Because texture state for SSBO read is setup as a single component
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* format (ie. R32_UINT, etc), we can't read more than the .x component
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* in one shot. Maybe there is some way we could mangle the state to
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* read more than one component at a shot, which would result is some-
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* what less register usage (given how we have to stick in the dummy
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* .y coord) and less alu instructions to calc offsets. But this is
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* also what blob does, so meh?
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*/
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for (unsigned i; i < intr->num_components; i++) {
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struct ir3_instruction *coords[2];
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coords[0] = (i == 0) ? offset :
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ir3_ADD_U(b, offset, 0, create_immed(b, i), 0);
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coords[1] = create_immed(b, 0);
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sam = ir3_SAM(b, OPC_ISAM, TYPE_U32, 0b1, 0,
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tex_idx, tex_idx, ir3_create_collect(ctx, coords, 2), NULL);
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sam->barrier_class = IR3_BARRIER_IMAGE_R;
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sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
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dst[i] = sam;
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}
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}
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/* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
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static void
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emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *stib, *val, *offset;
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nir_const_value *buffer_index;
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/* TODO handle wrmask properly, see _store_shared().. but I think
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* it is more a PITA than that, since blob ends up loading the
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* masked components and writing them back out.
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*/
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unsigned wrmask = intr->const_index[0];
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unsigned ncomp = ffs(~wrmask) - 1;
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/* can this be non-const buffer_index? how do we handle that? */
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buffer_index = nir_src_as_const_value(intr->src[1]);
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compile_assert(ctx, buffer_index);
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int ibo_idx = ir3_ssbo_to_ibo(&ctx->so->image_mapping, buffer_index->u32[0]);
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/* src0 is offset, src1 is value:
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*/
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val = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
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offset = ssbo_offset(b, ir3_get_src(ctx, &intr->src[2])[0]);
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stib = ir3_STIB(b, create_immed(b, ibo_idx), 0, offset, 0, val, 0);
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stib->cat6.iim_val = ncomp;
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stib->cat6.d = 1;
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stib->cat6.type = TYPE_U32;
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stib->barrier_class = IR3_BARRIER_BUFFER_W;
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stib->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
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array_insert(b, b->keeps, stib);
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}
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/*
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* SSBO atomic intrinsics
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*
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* All of the SSBO atomic memory operations read a value from memory,
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* compute a new value using one of the operations below, write the new
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* value to memory, and return the original value read.
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*
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* All operations take 3 sources except CompSwap that takes 4. These
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* sources represent:
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*
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* 0: The SSBO buffer index.
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* 1: The offset into the SSBO buffer of the variable that the atomic
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* operation will operate on.
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* 2: The data parameter to the atomic function (i.e. the value to add
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* in ssbo_atomic_add, etc).
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* 3: For CompSwap only: the second data parameter.
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*/
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static struct ir3_instruction *
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emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *atomic, *ibo, *src0, *src1, *offset, *data, *dummy;
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nir_const_value *buffer_index;
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type_t type = TYPE_U32;
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/* can this be non-const buffer_index? how do we handle that? */
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buffer_index = nir_src_as_const_value(intr->src[0]);
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compile_assert(ctx, buffer_index);
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int ibo_idx = ir3_ssbo_to_ibo(&ctx->so->image_mapping, buffer_index->u32[0]);
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ibo = create_immed(b, ibo_idx);
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offset = ir3_get_src(ctx, &intr->src[1])[0];
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data = ir3_get_src(ctx, &intr->src[2])[0];
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/* So this gets a bit creative:
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*
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* src0 - vecN offset/coords
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* src1.x - is actually destination register
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* src1.y - is 'data' except for cmpxchg where src2.y is 'compare'
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* src1.z - is 'data' for cmpxchg
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*
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* The combining src and dest kinda doesn't work out so well with how
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* scheduling and RA work. So for now we create a dummy src2.x, and
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* then in a later fixup path, insert an extra MOV out of src1.x.
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* See ir3_a6xx_fixup_atomic_dests().
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*
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* Note that nir already multiplies the offset by four
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*/
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dummy = create_immed(b, 0);
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src0 = ssbo_offset(b, offset);
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if (intr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
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struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[3])[0];
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src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
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dummy, compare, data
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}, 3);
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} else {
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src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
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dummy, data
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}, 2);
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}
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switch (intr->intrinsic) {
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case nir_intrinsic_ssbo_atomic_add:
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atomic = ir3_ATOMIC_ADD_G(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_imin:
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atomic = ir3_ATOMIC_MIN_G(b, ibo, 0, src0, 0, src1, 0);
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type = TYPE_S32;
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break;
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case nir_intrinsic_ssbo_atomic_umin:
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atomic = ir3_ATOMIC_MIN_G(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_imax:
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atomic = ir3_ATOMIC_MAX_G(b, ibo, 0, src0, 0, src1, 0);
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type = TYPE_S32;
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break;
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case nir_intrinsic_ssbo_atomic_umax:
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atomic = ir3_ATOMIC_MAX_G(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_and:
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atomic = ir3_ATOMIC_AND_G(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_or:
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atomic = ir3_ATOMIC_OR_G(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_xor:
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atomic = ir3_ATOMIC_XOR_G(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_exchange:
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atomic = ir3_ATOMIC_XCHG_G(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_comp_swap:
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atomic = ir3_ATOMIC_CMPXCHG_G(b, ibo, 0, src0, 0, src1, 0);
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break;
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default:
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unreachable("boo");
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}
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atomic->cat6.iim_val = 1;
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atomic->cat6.d = 1;
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atomic->cat6.type = type;
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atomic->barrier_class = IR3_BARRIER_BUFFER_W;
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atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
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/* even if nothing consume the result, we can't DCE the instruction: */
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array_insert(b, b->keeps, atomic);
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return atomic;
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}
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/* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
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static void
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emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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const nir_variable *var = nir_intrinsic_get_var(intr, 0);
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struct ir3_instruction *stib;
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struct ir3_instruction * const *value = ir3_get_src(ctx, &intr->src[3]);
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struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
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unsigned ncoords = ir3_get_image_coords(var, NULL);
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unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
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unsigned ibo_idx = ir3_image_to_ibo(&ctx->so->image_mapping, slot);
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unsigned ncomp = ir3_get_num_components_for_glformat(var->data.image.format);
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/* src0 is offset, src1 is value:
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*/
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stib = ir3_STIB(b, create_immed(b, ibo_idx), 0,
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ir3_create_collect(ctx, coords, ncoords), 0,
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ir3_create_collect(ctx, value, ncomp), 0);
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stib->cat6.iim_val = ncomp;
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stib->cat6.d = ncoords;
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stib->cat6.type = ir3_get_image_type(var);
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stib->cat6.typed = true;
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stib->barrier_class = IR3_BARRIER_IMAGE_W;
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stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
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array_insert(b, b->keeps, stib);
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}
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/* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
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static struct ir3_instruction *
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emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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const nir_variable *var = nir_intrinsic_get_var(intr, 0);
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struct ir3_instruction *atomic, *ibo, *src0, *src1, *dummy;
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struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
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struct ir3_instruction *value = ir3_get_src(ctx, &intr->src[3])[0];
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unsigned ncoords = ir3_get_image_coords(var, NULL);
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unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
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unsigned ibo_idx = ir3_image_to_ibo(&ctx->so->image_mapping, slot);
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ibo = create_immed(b, ibo_idx);
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|
/* So this gets a bit creative:
|
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|
*
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|
|
* src0 - vecN offset/coords
|
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|
* src1.x - is actually destination register
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|
* src1.y - is 'value' except for cmpxchg where src2.y is 'compare'
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|
* src1.z - is 'value' for cmpxchg
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|
*
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* The combining src and dest kinda doesn't work out so well with how
|
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* scheduling and RA work. So for now we create a dummy src2.x, and
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* then in a later fixup path, insert an extra MOV out of src1.x.
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|
* See ir3_a6xx_fixup_atomic_dests().
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|
*/
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dummy = create_immed(b, 0);
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|
src0 = ir3_create_collect(ctx, coords, ncoords);
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if (intr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap) {
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struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[4])[0];
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|
src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
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dummy, compare, value
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}, 3);
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} else {
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|
src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
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dummy, value
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|
}, 2);
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|
}
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|
|
switch (intr->intrinsic) {
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|
case nir_intrinsic_image_deref_atomic_add:
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|
atomic = ir3_ATOMIC_ADD_G(b, ibo, 0, src0, 0, src1, 0);
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|
break;
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|
case nir_intrinsic_image_deref_atomic_min:
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|
atomic = ir3_ATOMIC_MIN_G(b, ibo, 0, src0, 0, src1, 0);
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|
|
break;
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|
case nir_intrinsic_image_deref_atomic_max:
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|
atomic = ir3_ATOMIC_MAX_G(b, ibo, 0, src0, 0, src1, 0);
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|
|
break;
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|
|
case nir_intrinsic_image_deref_atomic_and:
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|
|
atomic = ir3_ATOMIC_AND_G(b, ibo, 0, src0, 0, src1, 0);
|
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|
|
break;
|
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|
|
case nir_intrinsic_image_deref_atomic_or:
|
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|
|
atomic = ir3_ATOMIC_OR_G(b, ibo, 0, src0, 0, src1, 0);
|
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|
|
|
break;
|
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|
|
case nir_intrinsic_image_deref_atomic_xor:
|
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|
|
|
atomic = ir3_ATOMIC_XOR_G(b, ibo, 0, src0, 0, src1, 0);
|
|
|
|
|
break;
|
|
|
|
|
case nir_intrinsic_image_deref_atomic_exchange:
|
|
|
|
|
atomic = ir3_ATOMIC_XCHG_G(b, ibo, 0, src0, 0, src1, 0);
|
|
|
|
|
break;
|
|
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|
|
case nir_intrinsic_image_deref_atomic_comp_swap:
|
|
|
|
|
atomic = ir3_ATOMIC_CMPXCHG_G(b, ibo, 0, src0, 0, src1, 0);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
unreachable("boo");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
atomic->cat6.iim_val = 1;
|
|
|
|
|
atomic->cat6.d = ncoords;
|
|
|
|
|
atomic->cat6.type = ir3_get_image_type(var);
|
|
|
|
|
atomic->cat6.typed = true;
|
|
|
|
|
atomic->barrier_class = IR3_BARRIER_IMAGE_W;
|
|
|
|
|
atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
|
|
|
|
|
|
|
|
|
|
/* even if nothing consume the result, we can't DCE the instruction: */
|
|
|
|
|
array_insert(b, b->keeps, atomic);
|
|
|
|
|
|
|
|
|
|
return atomic;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const struct ir3_context_funcs ir3_a6xx_funcs = {
|
|
|
|
|
.emit_intrinsic_load_ssbo = emit_intrinsic_load_ssbo,
|
|
|
|
|
.emit_intrinsic_store_ssbo = emit_intrinsic_store_ssbo,
|
|
|
|
|
.emit_intrinsic_atomic_ssbo = emit_intrinsic_atomic_ssbo,
|
|
|
|
|
.emit_intrinsic_store_image = emit_intrinsic_store_image,
|
|
|
|
|
.emit_intrinsic_atomic_image = emit_intrinsic_atomic_image,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Special pass to run after instruction scheduling to insert an
|
|
|
|
|
* extra mov from src1.x to dst. This way the other compiler passes
|
|
|
|
|
* can ignore this quirk of the new instruction encoding.
|
|
|
|
|
*
|
|
|
|
|
* This might cause extra complication in the future when we support
|
|
|
|
|
* spilling, as I think we'd want to re-run the scheduling pass. One
|
|
|
|
|
* possible alternative might be to do this in the RA pass after
|
|
|
|
|
* ra_allocate() but before destroying the SSA links. (Ie. we do
|
|
|
|
|
* want to know if anything consumes the result of the atomic instr,
|
|
|
|
|
* if there is no consumer then inserting the extra mov is pointless.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static struct ir3_instruction *
|
|
|
|
|
get_atomic_dest_mov(struct ir3_instruction *atomic)
|
|
|
|
|
{
|
|
|
|
|
/* if we've already created the mov-out, then re-use it: */
|
|
|
|
|
if (atomic->data)
|
|
|
|
|
return atomic->data;
|
|
|
|
|
|
|
|
|
|
/* extract back out the 'dummy' which serves as stand-in for dest: */
|
|
|
|
|
struct ir3_instruction *src = ssa(atomic->regs[3]);
|
|
|
|
|
debug_assert(src->opc == OPC_META_FI);
|
|
|
|
|
struct ir3_instruction *dummy = ssa(src->regs[1]);
|
|
|
|
|
|
|
|
|
|
struct ir3_instruction *mov = ir3_MOV(atomic->block, dummy, TYPE_U32);
|
|
|
|
|
|
|
|
|
|
mov->flags |= IR3_INSTR_SY;
|
|
|
|
|
|
|
|
|
|
/* it will have already been appended to the end of the block, which
|
|
|
|
|
* isn't where we want it, so fix-up the location:
|
|
|
|
|
*/
|
|
|
|
|
list_delinit(&mov->node);
|
|
|
|
|
list_add(&mov->node, &atomic->node);
|
|
|
|
|
|
|
|
|
|
/* And because this is after instruction scheduling, we don't really
|
|
|
|
|
* have a good way to know if extra delay slots are needed. For
|
|
|
|
|
* example, if the result is consumed by an stib (storeImage()) there
|
|
|
|
|
* would be no extra delay slots in place already, but 5 are needed.
|
|
|
|
|
* Just plan for the worst and hope nobody looks at the resulting
|
|
|
|
|
* code that is generated :-(
|
|
|
|
|
*/
|
|
|
|
|
struct ir3_instruction *nop = ir3_NOP(atomic->block);
|
|
|
|
|
nop->repeat = 5;
|
|
|
|
|
|
|
|
|
|
list_delinit(&nop->node);
|
|
|
|
|
list_add(&nop->node, &mov->node);
|
|
|
|
|
|
|
|
|
|
return atomic->data = mov;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so)
|
|
|
|
|
{
|
|
|
|
|
if (so->image_mapping.num_ibo == 0)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
|
|
|
|
|
list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
|
|
|
|
|
instr->data = NULL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
|
|
|
|
|
list_for_each_entry_safe (struct ir3_instruction, instr, &block->instr_list, node) {
|
|
|
|
|
struct ir3_register *reg;
|
|
|
|
|
|
|
|
|
|
foreach_src(reg, instr) {
|
|
|
|
|
struct ir3_instruction *src = ssa(reg);
|
|
|
|
|
|
|
|
|
|
if (!src)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (is_atomic(src->opc) && (src->flags & IR3_INSTR_G))
|
|
|
|
|
reg->instr = get_atomic_dest_mov(src);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
Rob Clark