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intel/elk: Remove Gfx9+ from Reg related code

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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
This commit is contained in:
Caio Oliveira
2024-02-13 10:10:01 -08:00
committed by Marge Bot
parent f170d8395b
commit 936528cda5
4 changed files with 6 additions and 204 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/elk/elk_ir_fs.h
+2 -7
View File
@@ -573,7 +573,7 @@ is_send(const elk_fs_inst *inst)
static inline bool
is_unordered(const intel_device_info *devinfo, const elk_fs_inst *inst)
{
return is_send(inst) || (devinfo->ver < 20 && inst->is_math()) ||
return is_send(inst) || inst->is_math() ||
(devinfo->has_64bit_float_via_math_pipe &&
(get_exec_type(inst) == ELK_REGISTER_TYPE_DF ||
inst->dst.type == ELK_REGISTER_TYPE_DF));
@@ -611,12 +611,7 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo,
if (type_sz(dst_type) > 4 || type_sz(exec_type) > 4 ||
(type_sz(exec_type) == 4 && is_dword_multiply))
return devinfo->platform == INTEL_PLATFORM_CHV ||
intel_device_info_is_9lp(devinfo) ||
devinfo->verx10 >= 125;
else if (elk_reg_type_is_floating_point(dst_type))
return devinfo->verx10 >= 125;
return devinfo->platform == INTEL_PLATFORM_CHV;
else
return false;
src/intel/compiler/elk/elk_reg.h
+2 -23
View File
@@ -263,34 +263,13 @@ struct elk_reg {
static inline unsigned
phys_nr(const struct intel_device_info *devinfo, const struct elk_reg reg)
{
if (devinfo->ver >= 20) {
if (reg.file == ELK_GENERAL_REGISTER_FILE)
return reg.nr / 2;
else if (reg.file == ELK_ARCHITECTURE_REGISTER_FILE &&
reg.nr >= ELK_ARF_ACCUMULATOR &&
reg.nr < ELK_ARF_FLAG)
return ELK_ARF_ACCUMULATOR + (reg.nr - ELK_ARF_ACCUMULATOR) / 2;
else
return reg.nr;
} else {
return reg.nr;
}
return reg.nr;
}
static inline unsigned
phys_subnr(const struct intel_device_info *devinfo, const struct elk_reg reg)
{
if (devinfo->ver >= 20) {
if (reg.file == ELK_GENERAL_REGISTER_FILE ||
(reg.file == ELK_ARCHITECTURE_REGISTER_FILE &&
reg.nr >= ELK_ARF_ACCUMULATOR &&
reg.nr < ELK_ARF_FLAG))
return (reg.nr & 1) * REG_SIZE + reg.subnr;
else
return reg.subnr;
} else {
return reg.subnr;
}
return reg.subnr;
}
static inline bool
src/intel/compiler/elk/elk_reg_type.c
+2 -166
View File
@@ -151,55 +151,6 @@ static const struct hw_type {
[ELK_REGISTER_TYPE_UB] = { ELK_HW_REG_TYPE_UB, INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, ELK_HW_IMM_TYPE_V },
[ELK_REGISTER_TYPE_UV] = { INVALID, ELK_HW_IMM_TYPE_UV },
}, gfx11_hw_type[] = {
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[ELK_REGISTER_TYPE_NF] = { GFX11_HW_REG_TYPE_NF, INVALID },
[ELK_REGISTER_TYPE_F] = { GFX11_HW_REG_TYPE_F, GFX11_HW_IMM_TYPE_F },
[ELK_REGISTER_TYPE_HF] = { GFX11_HW_REG_TYPE_HF, GFX11_HW_IMM_TYPE_HF },
[ELK_REGISTER_TYPE_VF] = { INVALID, GFX11_HW_IMM_TYPE_VF },
[ELK_REGISTER_TYPE_D] = { GFX11_HW_REG_TYPE_D, GFX11_HW_IMM_TYPE_D },
[ELK_REGISTER_TYPE_UD] = { GFX11_HW_REG_TYPE_UD, GFX11_HW_IMM_TYPE_UD },
[ELK_REGISTER_TYPE_W] = { GFX11_HW_REG_TYPE_W, GFX11_HW_IMM_TYPE_W },
[ELK_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
[ELK_REGISTER_TYPE_B] = { GFX11_HW_REG_TYPE_B, INVALID },
[ELK_REGISTER_TYPE_UB] = { GFX11_HW_REG_TYPE_UB, INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, GFX11_HW_IMM_TYPE_V },
[ELK_REGISTER_TYPE_UV] = { INVALID, GFX11_HW_IMM_TYPE_UV },
}, gfx12_hw_type[] = {
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) },
[ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) },
[ELK_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) },
[ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) },
[ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) },
[ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) },
[ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) },
[ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID },
[ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) },
[ELK_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) },
}, gfx125_hw_type[] = {
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[ELK_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_FLOAT(3), GFX12_HW_REG_TYPE_FLOAT(3) },
[ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) },
[ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) },
[ELK_REGISTER_TYPE_VF] = { INVALID, GFX12_HW_REG_TYPE_FLOAT(0) },
[ELK_REGISTER_TYPE_Q] = { GFX12_HW_REG_TYPE_SINT(3), GFX12_HW_REG_TYPE_SINT(3) },
[ELK_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3), GFX12_HW_REG_TYPE_UINT(3) },
[ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), GFX12_HW_REG_TYPE_SINT(2) },
[ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), GFX12_HW_REG_TYPE_UINT(2) },
[ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), GFX12_HW_REG_TYPE_SINT(1) },
[ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), GFX12_HW_REG_TYPE_UINT(1) },
[ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), INVALID },
[ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), INVALID },
[ELK_REGISTER_TYPE_V] = { INVALID, GFX12_HW_REG_TYPE_SINT(0) },
[ELK_REGISTER_TYPE_UV] = { INVALID, GFX12_HW_REG_TYPE_UINT(0) },
};
/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
@@ -257,60 +208,6 @@ static const struct hw_3src_type {
[ELK_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD },
[ELK_REGISTER_TYPE_DF] = { GFX7_3SRC_TYPE_DF },
[ELK_REGISTER_TYPE_HF] = { GFX8_3SRC_TYPE_HF },
}, gfx10_hw_3src_align1_type[] = {
#define E(x) ELK_ALIGN1_3SRC_EXEC_TYPE_##x
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[ELK_REGISTER_TYPE_DF] = { GFX10_ALIGN1_3SRC_REG_TYPE_DF, E(FLOAT) },
[ELK_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[ELK_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
[ELK_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
[ELK_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
[ELK_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
[ELK_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[ELK_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
[ELK_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
}, gfx11_hw_3src_type[] = {
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[ELK_REGISTER_TYPE_NF] = { GFX11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) },
[ELK_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[ELK_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
[ELK_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
[ELK_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
[ELK_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
[ELK_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[ELK_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
[ELK_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
}, gfx12_hw_3src_type[] = {
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), },
[ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), },
[ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), },
[ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), },
[ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), },
[ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
[ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), },
[ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), },
}, gfx125_hw_3src_type[] = {
[0 ... ELK_REGISTER_TYPE_LAST] = { INVALID },
[ELK_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_UINT(3), E(FLOAT), },
[ELK_REGISTER_TYPE_F] = { GFX12_HW_REG_TYPE_UINT(2), E(FLOAT), },
[ELK_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1), E(FLOAT), },
[ELK_REGISTER_TYPE_Q] = { GFX12_HW_REG_TYPE_SINT(3), E(INT), },
[ELK_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3), E(INT), },
[ELK_REGISTER_TYPE_D] = { GFX12_HW_REG_TYPE_SINT(2), E(INT), },
[ELK_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), },
[ELK_REGISTER_TYPE_W] = { GFX12_HW_REG_TYPE_SINT(1), E(INT), },
[ELK_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
[ELK_REGISTER_TYPE_B] = { GFX12_HW_REG_TYPE_SINT(0), E(INT), },
[ELK_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0), E(INT), },
#undef E
};
@@ -326,16 +223,7 @@ elk_reg_type_to_hw_type(const struct intel_device_info *devinfo,
{
const struct hw_type *table;
if (devinfo->verx10 >= 125) {
assert(type < ARRAY_SIZE(gfx125_hw_type));
table = gfx125_hw_type;
} else if (devinfo->ver >= 12) {
assert(type < ARRAY_SIZE(gfx12_hw_type));
table = gfx12_hw_type;
} else if (devinfo->ver >= 11) {
assert(type < ARRAY_SIZE(gfx11_hw_type));
table = gfx11_hw_type;
} else if (devinfo->ver >= 8) {
if (devinfo->ver >= 8) {
assert(type < ARRAY_SIZE(gfx8_hw_type));
table = gfx8_hw_type;
} else if (devinfo->ver >= 7) {
@@ -369,13 +257,7 @@ elk_hw_type_to_reg_type(const struct intel_device_info *devinfo,
{
const struct hw_type *table;
if (devinfo->verx10 >= 125) {
table = gfx125_hw_type;
} else if (devinfo->ver >= 12) {
table = gfx12_hw_type;
} else if (devinfo->ver >= 11) {
table = gfx11_hw_type;
} else if (devinfo->ver >= 8) {
if (devinfo->ver >= 8) {
table = gfx8_hw_type;
} else if (devinfo->ver >= 7) {
table = gfx7_hw_type;
@@ -426,29 +308,6 @@ elk_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo,
return table[type].reg_type;
}
/**
* Convert a elk_reg_type enumeration value into the hardware representation
* for a 3-src align1 instruction
*/
unsigned
elk_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo,
enum elk_reg_type type)
{
if (devinfo->verx10 >= 125) {
assert(type < ARRAY_SIZE(gfx125_hw_3src_type));
return gfx125_hw_3src_type[type].reg_type;
} else if (devinfo->ver >= 12) {
assert(type < ARRAY_SIZE(gfx12_hw_3src_type));
return gfx12_hw_3src_type[type].reg_type;
} else if (devinfo->ver >= 11) {
assert(type < ARRAY_SIZE(gfx11_hw_3src_type));
return gfx11_hw_3src_type[type].reg_type;
} else {
assert(type < ARRAY_SIZE(gfx10_hw_3src_align1_type));
return gfx10_hw_3src_align1_type[type].reg_type;
}
}
/**
* Convert the hardware representation for a 3-src align16 instruction into a
* elk_reg_type enumeration value.
@@ -475,29 +334,6 @@ elk_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
return INVALID_REG_TYPE;
}
/**
* Convert the hardware representation for a 3-src align1 instruction into a
* elk_reg_type enumeration value.
*/
enum elk_reg_type
elk_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type, unsigned exec_type)
{
const struct hw_3src_type *table =
(devinfo->verx10 >= 125 ? gfx125_hw_3src_type :
devinfo->ver >= 12 ? gfx12_hw_3src_type :
devinfo->ver >= 11 ? gfx11_hw_3src_type :
gfx10_hw_3src_align1_type);
for (enum elk_reg_type i = 0; i <= ELK_REGISTER_TYPE_LAST; i++) {
if (table[i].reg_type == hw_type &&
table[i].exec_type == exec_type) {
return i;
}
}
return INVALID_REG_TYPE;
}
/**
* Return the element size given a register type.
*/
src/intel/compiler/elk/elk_reg_type.h
-8
View File
@@ -184,18 +184,10 @@ unsigned
elk_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo,
enum elk_reg_type type);
unsigned
elk_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo,
enum elk_reg_type type);
enum elk_reg_type
elk_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type);
enum elk_reg_type
elk_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type, unsigned exec_type);
unsigned
elk_reg_type_to_size(enum elk_reg_type type);