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ac/surface: fix prt_first_mip_tail calculation for gfx9+

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Use firstMipIdInTail directly from addrlib which calculated this
in a different way:

Original way: either dimension size of mipmap should be less than
the tile size.

Addrlib way: all dimesion size of the mipmap should be less than
the tile size and at lest one dimension size should be less than
half of the tile size, so that all following mip levels can fit
in one tile and any commit for level in the mip tail also commit
for all levels in mip tail.

Theoretically either way is OK but addrlib way needs less care
about the mip tail commit and better align with the true memory
layout given by itself.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14223>
This commit is contained in:
Qiang Yu
2021-12-16 10:07:46 +08:00
parent 40928e452d
commit 92d810fa74
1 changed files with 1 additions and 6 deletions
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src/amd/common/ac_surface.c
+1 -6
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@@ -1648,12 +1648,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
surf->prt_tile_width = out.blockWidth;
surf->prt_tile_height = out.blockHeight;
for (surf->first_mip_tail_level = 0; surf->first_mip_tail_level < in->numMipLevels;
++surf->first_mip_tail_level) {
if(mip_info[surf->first_mip_tail_level].pitch < out.blockWidth ||
mip_info[surf->first_mip_tail_level].height < out.blockHeight)
break;
}
surf->first_mip_tail_level = out.firstMipIdInTail;
for (unsigned i = 0; i < in->numMipLevels; i++) {
surf->u.gfx9.prt_level_offset[i] = mip_info[i].macroBlockOffset + mip_info[i].mipTailOffset;