From 92d810fa74af894bcca5f75405637fa595357974 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 16 Dec 2021 10:07:46 +0800 Subject: [PATCH] ac/surface: fix prt_first_mip_tail calculation for gfx9+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use firstMipIdInTail directly from addrlib which calculated this in a different way: Original way: either dimension size of mipmap should be less than the tile size. Addrlib way: all dimesion size of the mipmap should be less than the tile size and at lest one dimension size should be less than half of the tile size, so that all following mip levels can fit in one tile and any commit for level in the mip tail also commit for all levels in mip tail. Theoretically either way is OK but addrlib way needs less care about the mip tail commit and better align with the true memory layout given by itself. Reviewed-by: Marek Olšák Signed-off-by: Qiang Yu Part-of: --- src/amd/common/ac_surface.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 20942a0120c..0eb3dd091a0 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1648,12 +1648,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ surf->prt_tile_width = out.blockWidth; surf->prt_tile_height = out.blockHeight; - for (surf->first_mip_tail_level = 0; surf->first_mip_tail_level < in->numMipLevels; - ++surf->first_mip_tail_level) { - if(mip_info[surf->first_mip_tail_level].pitch < out.blockWidth || - mip_info[surf->first_mip_tail_level].height < out.blockHeight) - break; - } + surf->first_mip_tail_level = out.firstMipIdInTail; for (unsigned i = 0; i < in->numMipLevels; i++) { surf->u.gfx9.prt_level_offset[i] = mip_info[i].macroBlockOffset + mip_info[i].mipTailOffset;