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i965: official name for GM45 chipset

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This commit is contained in:
Xiang, Haihao
2008-07-08 14:14:04 +08:00
parent a36bf890e8
commit 92c075eeb7
10 changed files with 33 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_clip_line.c
+1 -1
View File
@@ -148,7 +148,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_clip_init_clipmask(c);
/* -ve rhw workaround */
if (!BRW_IS_IGD(p->brw)) {
if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw))) {
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
src/mesa/drivers/dri/i965/brw_clip_state.c
+1 -1
View File
@@ -102,7 +102,7 @@ clip_unit_create_from_key(struct brw_context *brw,
clip.clip5.api_mode = BRW_CLIP_API_OGL;
clip.clip5.clip_mode = key->clip_mode;
if (BRW_IS_IGD(brw))
if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw))
clip.clip5.negative_w_clip_test = 1;
clip.clip6.clipper_viewport_state_ptr = 0;
src/mesa/drivers/dri/i965/brw_clip_tri.c
+1 -1
View File
@@ -536,7 +536,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
/* if -ve rhw workaround bit is set,
do cliptest */
if (!BRW_IS_IGD(p->brw)) {
if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw))) {
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
src/mesa/drivers/dri/i965/brw_defines.h
+7 -6
View File
@@ -804,7 +804,7 @@
#define CMD_STATE_BASE_ADDRESS 0x6101
#define CMD_STATE_INSN_POINTER 0x6102
#define CMD_PIPELINE_SELECT_965 0x6104
#define CMD_PIPELINE_SELECT_IGD 0x6904
#define CMD_PIPELINE_SELECT_GM45 0x6904
#define CMD_PIPELINED_STATE_POINTERS 0x7800
#define CMD_BINDING_TABLE_PTRS 0x7801
@@ -836,7 +836,7 @@
#define CMD_INDEX_BUFFER 0x780a
#define CMD_VF_STATISTICS_965 0x780b
#define CMD_VF_STATISTICS_IGD 0x680b
#define CMD_VF_STATISTICS_GM45 0x680b
#define CMD_DRAW_RECT 0x7900
#define CMD_BLEND_CONSTANT_COLOR 0x7901
@@ -862,9 +862,10 @@
#include "intel_chipset.h"
#define BRW_IS_IGD(brw) (IS_IGD((brw)->intel.intelScreen->deviceID))
#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_IGD(brw)) ? CMD_PIPELINE_SELECT_IGD : CMD_PIPELINE_SELECT_965)
#define CMD_VF_STATISTICS(brw) ((BRW_IS_IGD(brw)) ? CMD_VF_STATISTICS_IGD : CMD_VF_STATISTICS_965)
#define URB_SIZES(brw) ((BRW_IS_IGD(brw)) ? 384 : 256) /* 512 bit unit */
#define BRW_IS_GM45(brw) (IS_GM45_GM((brw)->intel.intelScreen->deviceID))
#define BRW_IS_G4X(brw) (IS_G4X((brw)->intel.intelScreen->deviceID))
#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? CMD_PIPELINE_SELECT_GM45 : CMD_PIPELINE_SELECT_965)
#define CMD_VF_STATISTICS(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? CMD_VF_STATISTICS_GM45 : CMD_VF_STATISTICS_965)
#define URB_SIZES(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? 384 : 256) /* 512 bit unit */
#endif
src/mesa/drivers/dri/i965/brw_eu_emit.c
+8 -8
View File
@@ -329,14 +329,14 @@ static void brw_set_sampler_message(struct brw_context *brw,
{
brw_set_src1(insn, brw_imm_d(0));
if (BRW_IS_IGD(brw)) {
insn->bits3.sampler_igd.binding_table_index = binding_table_index;
insn->bits3.sampler_igd.sampler = sampler;
insn->bits3.sampler_igd.msg_type = msg_type;
insn->bits3.sampler_igd.response_length = response_length;
insn->bits3.sampler_igd.msg_length = msg_length;
insn->bits3.sampler_igd.end_of_thread = eot;
insn->bits3.sampler_igd.msg_target = BRW_MESSAGE_TARGET_SAMPLER;
if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) {
insn->bits3.sampler_gm45_g4x.binding_table_index = binding_table_index;
insn->bits3.sampler_gm45_g4x.sampler = sampler;
insn->bits3.sampler_gm45_g4x.msg_type = msg_type;
insn->bits3.sampler_gm45_g4x.response_length = response_length;
insn->bits3.sampler_gm45_g4x.msg_length = msg_length;
insn->bits3.sampler_gm45_g4x.end_of_thread = eot;
insn->bits3.sampler_gm45_g4x.msg_target = BRW_MESSAGE_TARGET_SAMPLER;
} else {
insn->bits3.sampler.binding_table_index = binding_table_index;
insn->bits3.sampler.sampler = sampler;
src/mesa/drivers/dri/i965/brw_misc_state.c
+4 -4
View File
@@ -192,7 +192,7 @@ static void emit_depthbuffer(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
struct intel_region *region = brw->state.depth_region;
unsigned int len = BRW_IS_IGD(brw) ? sizeof(struct brw_depthbuffer_igd) / 4 : sizeof(struct brw_depthbuffer) / 4;
unsigned int len = (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? sizeof(struct brw_depthbuffer_gm45_g4x) / 4 : sizeof(struct brw_depthbuffer) / 4;
if (region == NULL) {
BEGIN_BATCH(len, IGNORE_CLIPRECTS);
@@ -203,7 +203,7 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(0);
OUT_BATCH(0);
if (BRW_IS_IGD(brw))
if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw))
OUT_BATCH(0);
ADVANCE_BATCH();
@@ -239,7 +239,7 @@ static void emit_depthbuffer(struct brw_context *brw)
((region->height - 1) << 19));
OUT_BATCH(0);
if (BRW_IS_IGD(brw))
if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw))
OUT_BATCH(0);
ADVANCE_BATCH();
@@ -324,7 +324,7 @@ static void upload_aa_line_parameters(struct brw_context *brw)
{
struct brw_aa_line_parameters balp;
if (!BRW_IS_IGD(brw))
if (!(BRW_IS_GM45(brw) || BRW_IS_G4X(brw)))
return;
/* use legacy aa line coverage computation */
src/mesa/drivers/dri/i965/brw_structs.h
+2 -2
View File
@@ -175,7 +175,7 @@ struct brw_depthbuffer
} dword4;
};
struct brw_depthbuffer_igd
struct brw_depthbuffer_gm45_g4x
{
union header_union header;
@@ -1405,7 +1405,7 @@ struct brw_instruction
GLuint msg_target:4;
GLuint pad1:3;
GLuint end_of_thread:1;
} sampler_igd;
} sampler_gm45_g4x;
struct brw_urb_immediate urb;
src/mesa/drivers/dri/i965/brw_vs_emit.c
+1 -1
View File
@@ -867,7 +867,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
* Later, clipping will detect ucp[6] and ensure the primitive is
* clipped against all fixed planes.
*/
if (!BRW_IS_IGD(p->brw) && !c->key.know_w_is_one) {
if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw)) && !c->key.know_w_is_one) {
brw_CMP(p,
vec8(brw_null_reg()),
BRW_CONDITIONAL_L,
src/mesa/drivers/dri/intel/intel_chipset.h
+5 -5
View File
@@ -53,7 +53,7 @@
#define PCI_CHIP_I965_GM 0x2A02
#define PCI_CHIP_I965_GME 0x2A12
#define PCI_CHIP_IGD_GM 0x2A42
#define PCI_CHIP_GM45_GM 0x2A42
#define PCI_CHIP_IGD_E_G 0x2E02
#define PCI_CHIP_Q45_G 0x2E12
@@ -65,13 +65,12 @@
devid == PCI_CHIP_I945_GME || \
devid == PCI_CHIP_I965_GM || \
devid == PCI_CHIP_I965_GME || \
devid == PCI_CHIP_IGD_GM)
devid == PCI_CHIP_GM45_GM)
#define IS_IGD_GM(devid) (devid == PCI_CHIP_IGD_GM)
#define IS_GM45_GM(devid) (devid == PCI_CHIP_GM45_GM)
#define IS_G4X(devid) (devid == PCI_CHIP_IGD_E_G || \
devid == PCI_CHIP_Q45_G || \
devid == PCI_CHIP_G45_G)
#define IS_IGD(devid) (IS_IGD_GM(devid) || IS_G4X(devid))
#define IS_915(devid) (devid == PCI_CHIP_I915_G || \
devid == PCI_CHIP_E7221_G || \
@@ -90,7 +89,8 @@
devid == PCI_CHIP_I965_GM || \
devid == PCI_CHIP_I965_GME || \
devid == PCI_CHIP_I946_GZ || \
IS_IGD(devid))
IS_GM45_GM(devid) || \
IS_G4X(devid))
#define IS_9XX(devid) (IS_915(devid) || \
IS_945(devid) || \
src/mesa/drivers/dri/intel/intel_context.c
+3 -1
View File
@@ -166,7 +166,9 @@ intelGetString(GLcontext * ctx, GLenum name)
case PCI_CHIP_I965_GME:
chipset = "Intel(R) 965GME/GLE";
break;
case PCI_CHIP_IGD_GM:
case PCI_CHIP_GM45_GM:
chipset = "Mobile Intel® GM45 Express Chipset";
break;
case PCI_CHIP_IGD_E_G:
chipset = "Intel(R) Integrated Graphics Device";
break;